A VLSI 128-channel data link control

A controller with a 160K transistor automatically extracted from a behavorial description and fabricated in 1μm CMOS will be described. The chip is 367×390 mils, attaining a device density of 0.9mil2per transistor and dissipates 600mW at a clock rate of 8MHz.

[1]  Sunil Jain,et al.  Built-in Self Testing of Embedded Memories , 1986, IEEE Design & Test of Computers.