Formal Development of NoC Systems in B

When developing complex Network-on-Chip (NoC) systems we need to ensure that they satisfy their functional requirements. This can be achieved by developing the systems in a structured way using a formal method with tool support. We use the B Action Systems formalism for this purpose. We give a general formal framework for the development of NoC systems avoiding architectures with complex controllers and complex arbiter modules for deciding the routing path of a data packet. The development is performed in a stepwise manner composing more advanced routing components out of simpler units.

[1]  F. Arbab,et al.  Coordination through Channel Composition , 2002, COORDINATION.

[2]  Lionel M. Ni,et al.  A survey of wormhole routing techniques in direct networks , 1993, Computer.

[3]  Kaisa Sere,et al.  From Action Systems to Modular Systems , 1994, Softw. Concepts Tools.

[4]  Kaisa Sere,et al.  Reasoning about Action Systems using the B-Method , 1998, Formal Methods Syst. Des..

[5]  Edsger W. Dijkstra,et al.  A Discipline of Programming , 1976 .

[6]  Shmuel Katz,et al.  A superimposition control construct for distributed systems , 1993, TOPL.

[7]  Axel Jantsch,et al.  Network on Chip : An architecture for billion transistor era , 2000 .

[8]  Ralph-Johan Back,et al.  Decentralization of Process Nets with Centralized Control , 1983, PODC.

[9]  Marina Waldén Distributed Load Balancing , 1999 .

[10]  Sujit Dey,et al.  On-chip communication architecture for OC-768 network processors , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[11]  Kaisa Sere,et al.  Asynchronous system synthesis , 2005, Sci. Comput. Program..

[12]  A. Jantsch,et al.  Low-power and error coding for network-on-chip traffic , 2004, Proceedings Norchip Conference, 2004..

[13]  Radu Marculescu,et al.  DyAD - smart routing for networks-on-chip , 2004, Proceedings. 41st Design Automation Conference, 2004..

[14]  Kaisa Sere,et al.  Data Refinement of Remote Procedures , 2000, Formal Aspects of Computing.

[15]  Axel Jantsch,et al.  Load distribution with the proximity congestion awareness in a network on chip , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[16]  Ge-Ming Chiu,et al.  The Odd-Even Turn Model for Adaptive Routing , 2000, IEEE Trans. Parallel Distributed Syst..

[17]  Ralph-Johan Back,et al.  Compositional Action System Refinement , 2003, Formal Aspects of Computing.

[18]  Jean-Raymond Abrial,et al.  The B-book - assigning programs to meanings , 1996 .

[19]  Julien Schmaltz,et al.  TheoSim: combining symbolic simulation and theorem proving for hardware verification , 2004, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784).

[20]  Ad M. G. Peeters,et al.  Single-rail handshake circuits , 1995, Proceedings Second Working Conference on Asynchronous Design Methodologies.

[21]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[22]  William J. Dally,et al.  Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.

[23]  Michael Butler,et al.  Distributed System Development in B , 1996 .

[24]  Julien Schmaltz,et al.  A Functional Approach to the Formal Specification of Networks on Chip , 2004, FMCAD.

[25]  Kees G. W. Goossens,et al.  Deadlock Prevention in the Æthereal Protocol , 2005, CHARME.