Unrestricted vs restricted cut in a tableau method for Boolean circuits

AbstractThis paper studies the relative efficiency of variations of a tableau method for Boolean circuit satisfiability checking. The considered method is a nonclausal generalisation of the Davis–Putnam–Logemann–Loveland (DPLL) procedure to Boolean circuits. The variations are obtained by restricting the use of the cut (splitting) rule in several natural ways. It is shown that the more restricted variations cannot polynomially simulate the less restricted ones. For each pair of methods T, T′, an infinite family $\{\mathcal{C}_{n}\}$ of circuits is devised for which T has polynomial size proofs while in T′ the minimal proofs are of exponential size w.r.t. n, implying exponential separation of T and T′ w.r.t. n. The results also apply to DPLL for formulas in conjunctive normal form obtained from Boolean circuits by using Tseitin’s translation. Thus DPLL with the considered cut restrictions, such as allowing splitting only on the variables corresponding to the input gates, cannot polynomially simulate DPLL with unrestricted splitting.

[1]  David A. Plaisted,et al.  A Structure-Preserving Clause Form Translation , 1986, J. Symb. Comput..

[2]  Armin Biere,et al.  Bounded Model Checking Using Satisfiability Solving , 2001, Formal Methods Syst. Des..

[3]  Tracy Larrabee,et al.  Test pattern generation using Boolean satisfiability , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Jon M. Kleinberg,et al.  A deterministic (2-2/(k+1))n algorithm for k-SAT based on local search , 2002, Theor. Comput. Sci..

[5]  E. V. Nuttall.  ACT , 1986 .

[6]  Sharad Malik,et al.  Chaff: engineering an efficient SAT solver , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[7]  Ofer Shtrichman.  Tuning SAT Checkers for Bounded Model Checking , 2000, CAV 2000.

[8]  Malay K. Ganai,et al.  Circuit-based Boolean reasoning , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[9]  Stasys Jukna.  Extremal Combinatorics: with Applications in Computer Science by Stasys Jukna, Springer, 2001, xvii + 375 pp. 32.50; $49.95, ISBN 3540663134 , 2003 .

[10]  Henry Kautz,et al.  Pushing the envelope: planning , 1996 .

[11]  Toniann Pitassi,et al.  Propositional Proof Complexity: Past, Present and Future , 2001, Bull. EATCS.

[12]  Joao Marques-Silva,et al.  GRASP-A new search algorithm for satisfiability , 1996, Proceedings of International Conference on Computer Aided Design.

[13]  Joao Marques-Silva,et al.  Solving satisfiability in combinational circuits , 2003, IEEE Design & Test of Computers.

[14]  Ofer Strichman,et al.  Tuning SAT Checkers for Bounded Model Checking , 2000, CAV.

[15]  Bart Selman,et al.  Planning as Satisfiability , 1992, ECAI.

[16]  Michael E. Saks,et al.  The Efficiency of Resolution and Davis--Putnam Procedures , 2002, SIAM J. Comput..

[17]  Marcello D'Agostino,et al.  The Taming of the Cut. Classical Refutations with Analytic Cut , 1994, J. Log. Comput..

[18]  JärvisaloMatti,et al.  Unrestricted vs restricted cut in a tableau method for Boolean circuits , 2005 .

[19]  Donald W. Loveland,et al.  A machine program for theorem-proving , 2011, CACM.

[20]  Enrico Giunchiglia,et al.  Applying the Davis-Putnam Procedure to Non-clausal Formulas , 1999, AI*IA.

[21]  Sharad Malik,et al.  The Quest for Efficient Boolean Satisfiability Solvers , 2002, CAV.

[22]  Armin Haken,et al.  The Intractability of Resolution , 1985, Theor. Comput. Sci..

[23]  Toby Walsh,et al.  Solving Non-clausal Formulas with DPLL search , 2004, SAT.

[24]  Sharad Malik,et al.  The Quest for Efficient Boolean Satisfiability Solvers , 2002, CAV.

[25]  Enrico Giunchiglia,et al.  Act, and the Rest Will Follow: Exploiting Determinism in Planning as Satisfiability , 1998, AAAI/IAAI.

[26]  Jun Gu,et al.  Algorithms for the satisfiability (SAT) problem: A survey , 1996, Satisfiability Problem: Theory and Applications.

[27]  Karem A. Sakallah,et al.  GRASP—a new search algorithm for satisfiability , 1996, ICCAD 1996.

[28]  Hilary Putnam,et al.  A Computing Procedure for Quantification Theory , 1960, JACM.

[29]  Fabio Massacci.  Simplification: A General Constraint Propagation Technique for Propositional and Modal Tableaux , 1998, TABLEAUX.

[30]  Sharad Malik,et al.  Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver , 2002, DAC '02.

[31]  Sharad Malik,et al.  Efficient conflict driven learning in a Boolean satisfiability solver , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[32]  Bart Selman,et al.  Local search strategies for satisfiability testing , 1993, Cliques, Coloring, and Satisfiability.

[33]  Wolfgang Kunz,et al.  SAT and ATPG: Boolean engines for formal hardware verification , 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

[34]  Ilkka Niemelä,et al.  Towards an Efficient Tableau Method for Boolean Circuit Satisfiability Checking , 2000, Computational Logic.

[35]  D. Gabbay,et al.  Handbook of tableau methods , 1999 .

[36]  Bart Selman,et al.  Pushing the Envelope: Planning, Propositional Logic and Stochastic Search , 1996, AAAI/IAAI, Vol. 2.

[37]  Stephen A. Cook,et al.  The Relative Efficiency of Propositional Proof Systems , 1979, Journal of Symbolic Logic.

[38]  J. A. Robinson,et al.  A Machine-Oriented Logic Based on the Resolution Principle , 1965, JACM.

[39]  Per Bjesse,et al.  Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers , 2001, CAV.

[40]  G. S. Tseitin.  On the Complexity of Derivation in Propositional Calculus , 1983 .