High-Speed ADC Building Blocks in 90 nm CMOS

A sample & hold circuit, a comparator and a decision flip-flop are implemented in 90 nm standard CMOS technology. The input switch of the sample & hold circuit provides a bandwidth in excess of 30 GHz at a sampling rate of 10 Gs/s. The limiting amplifier based comparator with active peaking performs slicing of 10 Gbaud signals with a 5%-to-95% settling time of 43 ps. A decision flip-flop provides a phase margin of 324° at 200 mV and 274° at 50 mV input signal swing. All blocks are implemented without any spiral inductors. The building block performance indicates the feasibility of a 40-Gs/s 3-bit flash analog-to-digital converter with 4-fold time-interleaved architecture.