Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits

The application of scan-based at-speed delay testing on asynchronous circuits is not trivial. Their unorthodox design leaves them generally incompatible with traditional synchronous design and test tools, as well as standard automatic test equipment. The correct generation of at-speed test clocks and the use of conventional automatic test patterns generation (ATPG) tools are some of the problems that face the application of at-speed testing on asynchronous circuits. This paper presents a method of applying scan-based at-speed testing on single-rail bundleddata handshake-free (self-timed) asynchronous circuits by taking advantage of built-in delay lines. The proposed test method uses launch-on-capture scan-based testing with endpoint masking and generates the test patterns using conventional ATPG tools. The proposed test is applied on circuits in a self-timed microprocessor fabricated in 28nm FD-SOI CMOS technology. This method is validated by the reported test coverage and simulation results, along with post-silicon test results on a Teradyne FLEX tester.

[1]  Hans G. Kerkhoff,et al.  Automatic scan insertion and test generation for asynchronous circuits , 2002, Proceedings. International Test Conference.

[2]  Yvon Savaria,et al.  Self-timed circuits FPGA implementation flow , 2015, 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS).

[3]  Feng Shi,et al.  Testing Delay Faults in Asynchronous Handshake Circuits , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[4]  Srinivas Patil,et al.  Broad-side delay test , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Janusz Rajski,et al.  High-frequency, at-speed scan testing , 2003, IEEE Design & Test of Computers.

[6]  Feng Shi,et al.  Low-overhead testing of delay faults in high-speed asynchronous pipelines , 2006, 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06).

[7]  Jacob Savir,et al.  Skewed-Load Transition Test: Part I, Calculus , 1992, Proceedings International Test Conference 1992.

[8]  Ad M. G. Peeters,et al.  A multiplexer based test method for self-timed circuits , 2005, 11th IEEE International Symposium on Asynchronous Circuits and Systems.

[9]  Alexandre Yakovlev,et al.  Advances in asynchronous logic: From principles to GALS & NoC, recent industry applications, and commercial CAD tools , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[10]  Michel Laurence Introduction to Octasic Asynchronous Processor Technology , 2012, 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems.