Automated Verification of State-based specifications against scenarios (A step toward relating in

While designing a system, it is critical to ensure that its behavioral speci cation is correct with respect to its requirements. These requirements are often described as a set of scenarios instantiating use-cases. Formal and automated veri cation of this correctness is desirable in this context. To formally describe scenarios, we use LSCs [Harel 98a], an extension of Message Sequence Charts (MSCs) allowing the expression of both safety and liveness conditions. An algorithm to automatically translate LSCs into temporal logic is presented. The obtained formulae can then be used by a model-checker to prove the correctness of the speci cation. Hence, a total automation of the veri cation process is obtained. To achieve a better e ciency in veri cation, we then re ne the translation, by splitting the formula into several smaller formulae. Again, we exhibit an algorithmic solution to support these methods.