A CMOS Voltage Reference Based on Weighted V GS for CMOS Low-Dropout Linear Regulators

A CMOS voltage reference, which is based on the weighted difference of the gate–source voltages of an NMOST and a PMOST operating in saturation region, is presented. The voltage reference is designed for CMOS low-dropout linear regulators and has been implemented in a standard 0.6-m CMOS technology ( 0 9 V at 0 C). The occupied chip area is 0.055 mm. The minimum supply voltage is 1.4 V, and the maximum supply current is 9.7 A. A typical mean uncalibrated temperature coefficient of 36.9 ppm C is achieved, and the typical mean line regulation is 0.083% V. The power-supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz are 47 and 20 dB, respectively. Moreover, the measured noise density with a 100-nF filtering capacitor at 100 Hz is 152 nV Hz and that at 100 kHz is 1.6 nV Hz.

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