Tunneling into interface states as reliability monitor for ultrathin oxides
暂无分享,去创建一个
Enrico Sangiorgi | A. Ghetti | J. Bude | G. Weber | T. W. Sorsch | J. Bude | A. Ghetti | E. Sangiorgi | T. Sorsch | G. Weber
[1] G. Alers,et al. Intrinsic and stress-induced traps in the direct tunneling current of 2.3-3.8 nm oxides and unified characterization methodologies of sub-3 nm oxides , 1997, International Electron Devices Meeting. IEDM Technical Digest.
[2] C. Liu,et al. Circuit requirement and integration challenges of thin gate dielectrics for ultra small MOSFETs , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).
[3] R. Pierret,et al. Advanced semiconductor fundamentals , 1987 .
[4] A. Ghetti,et al. An anode hole injection percolation model for oxide breakdown-the "doom's day" scenario revisited , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).
[5] J. Brini,et al. On the tunneling component of charge pumping current in ultrathin gate oxide MOSFETs , 1999, IEEE Electron Device Letters.
[6] James H. Stathis,et al. On the relationship between stress induced leakage currents and catastrophic breakdown in ultra-thin SiO2 based dielectrics , 1997 .
[7] Guido Groeseneken,et al. New insights in the relation between electron trap generation and the statistical properties of oxide breakdown , 1998 .
[8] A. Ghetti,et al. Progress toward 10 nm CMOS devices , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).
[9] Marvin H. White,et al. Observation and characterization of near-interface oxide traps with C-V techniques , 1995 .
[10] I. C. Kizilyalli,et al. Three-dimensional characterization of bipolar transistors in a submicron BiCMOS technology using integrated process and device simulation , 1992, 1992 International Technical Digest on Electron Devices Meeting.
[11] T. Sugii,et al. A Direct Tunneling Memory (DTM) utilizing novel floating gate structure , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).
[12] J. Stathis,et al. Ultimate limit for defect generation in ultra-thin silicon dioxide , 1997 .
[13] J. Stathis,et al. Reliability projection for ultra-thin oxides at low voltage , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).
[14] Bruno Ricco,et al. Modeling and simulation of stress-induced leakage current in ultrathin SiO/sub 2/ films , 1998 .
[15] E. Sangiorgi,et al. The role of native traps on the tunneling characteristics of ultrathin (1.5-3 nm) oxides , 1999 .
[16] Yuan Taur,et al. CMOS scaling into the 21st century: 0.1 µm and beyond , 1995, IBM J. Res. Dev..
[17] Robert M. Wallace,et al. Low voltage stress-induced-leakage-current in ultrathin gate oxides , 1999, 1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296).
[18] S. M. Sze,et al. Physics of semiconductor devices , 1969 .
[19] G. Groeseneken,et al. A reliable approach to charge-pumping measurements in MOS transistors , 1984, IEEE Transactions on Electron Devices.
[20] E. Sangiorgi,et al. Low voltage tunneling in ultra-thin oxides: a monitor for interface states and degradation , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).
[21] L. Register,et al. Trap-assisted tunneling current through ultra-thin oxide , 1999, 1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296).
[22] H. Vaidya,et al. Self-consistent simulation of quantization effects and tunneling current in ultra-thin gate oxide MOS devices , 1999, 1999 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD'99 (IEEE Cat. No.99TH8387).
[23] J. Wortman,et al. Analysis of tunneling currents and reliability of NMOSFETs with sub-2 nm gate oxides , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).
[24] G. Lucovsky,et al. Time dependent dielectric wearout (TDDW) technique for reliability of ultrathin gate oxides , 1999, IEEE Electron Device Letters.
[25] M. Depas,et al. Relation between trap creation and breakdown during tunnelling current stressing of Sub 3 nm gate oxide , 1997 .