High Gain Low Power Operational Amplifier Design and Compensation Techniques

HIGH GAIN LOW POWER OPERATIONAL AMPLIFIER DESIGN AND COMPENSATION TECHNIQUES Lisha Li Department of Electrical and Computer Engineering Doctor of Philosophy This dissertation discusses and compares the existing compensation methods for operational amplifiers. It explores a method to stabilize the op amps without sacrificing bandwidth to the same degree that commonly used methods do. A creative design methodology combining intuition, mathematical analysis, and mixed level simulation is explored for the new compensation scheme. The mixed level approach, associating system level simulation for most circuits along with device level simulation for some critical analog circuit paths, is presented to verify the behavior of new design concepts in an effective way. This approach also provides sufficient accuracy to predict the circuit performance realistically. The new feedforward compensation method overcomes the serious drawback of the widely used pole splitting method, which greatly narrows the bandwidth. It can improve the phase margin as well as optimize the bandwidth of the op amp. The proposed feedforward compensation method can be easily applied to the popular two gain stage op amp architectures with very little alteration. MOS devices are used in the weak inversion region or the subthreshold inversion region to minimize dc source power. A feasible configuration for high gain, low power op amp design utilizing subthreshold operation along with active operation is proposed. This op amp uses composite cascode connections for the differential input stage, a common source second stage, and a current mirror. A prototype of the op amp was fabricated in a 0.25 μm CMOS process. The proposed op amp produces an open loop gain above one million with low power consumption around 110 μW and shows a favorable slew rate and GBW product compared to other amplifiers driving large capacitive loads. In addition, the composite cascode amplifier requires a compensation capacitor of only 3.5 pF which allows a very small op amp cell. This design is intended for applications where simplicity of layout, small cell size, and low power are important. The open loop gain of this design is comparable to bipolar op amps and exceeds all known reported CMOS designs using the classic Widlar architecture. The fabricated op amp test results show that the BSIM3 model in CADENCE Spectre Spice Simulation matches closely to the experimental results in spite of the low current weak inversion operation of the composite cascode output device and thus provide confidence in the simulation for other similar designs. While facing the challenge of measuring the op amp open loop characteristics at decreased power supply voltages, a few viable techniques were developed to measure the op amp open loop parameters using typically available bench test equipment.