Ultra-Shallow Junction Formation with Antimony Implantation

SUMMARY Ultra shallow low-resistive junction formation has been investigated for sub-100-nm MOSFETs using antimony implantation. The pileup at the Si/SiO2 interface and the resulting dopant loss during annealing is a common obstacle for antimonyand arsenic to reduce junction sheet resistance. Though implanted arsenic gives rise to pileup even with a few seconds duration RTA (Rapid Thermal Annealing), antimonypileup was suppressed with the RTA at relativelylow temperature, such as 800 ◦ C or 900 ◦ C. As a result, low sheet resistance of 260 Ω/sq. was obtained for a 24 nm depth junction with antimony. These results indicate that antimonyis superior to arsenic as a dopant for ultra shallow extension formation. However, increase in antimonyconcentration above 1 × 1020 cm−3 gives rise to precipitation and it limits the sheet resistance reduction of the antimony doped junctions. Redistribution behaviors of antimonyrelating to the pileup and the precipitation are discussed utilizing SIMS (SecondaryIon Mass Spectrometry ) depth profiles.

[1]  D. Moy,et al.  Experimental technology and characterization of self-aligned 0.1µm-gate-length low-temperature operation NMOS devices , 1987, 1987 International Electron Devices Meeting.

[2]  Kentaro Shibahara,et al.  Antimony Clustering due to High-dose Implantation , 2000 .

[3]  K. Shibahara,et al.  Low resistive ultra shallow junction for sub 0.1 /spl mu/m MOSFETs formed by Sb implantation , 1996, International Electron Devices Meeting. Technical Digest.

[4]  T. Kanemura,et al.  ANOMALOUS DIFFUSION OF LIGHTLY IMPLANTED AS INTO SI SUBSTRATE DURING N2 ANNEALING , 1994 .

[5]  Y. Taur,et al.  High transconductance 0.1 mu m pMOSFET , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[6]  Kentaro Shibahara,et al.  Improvement in Antimony-Doped Ultrashallow Junction Sheet Resistance by Dopant Pileup Reduction at the SiO2/Si Interface , 2000 .

[7]  Shin Yokoyama,et al.  Quantitative Evaluation of Dopant Loss in 5 10 keV As Ion Implantation for Low-Resistive, Ultrashallow Source/Drain Formation , 1999 .

[8]  G. Sai-Halasz,et al.  Device-grade ultra-shallow junctions fabricated with antimony , 1986, IEEE Electron Device Letters.

[9]  K. Shibahara,et al.  Dopant Loss Origins of Low Energy Implanted Arsenic and Antimony for Ultra Shallow Junction Formation , 1998 .

[10]  M. Takayanagi,et al.  Optimized halo structure for 80 nm physical gate CMOS technology with indium and antimony highly angled ion implantation , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[11]  P. Griffin,et al.  Characterization of arsenic dose loss at the Si/SiO2 interface , 2000 .

[12]  E. Nowak,et al.  A high-performance 0.08 /spl mu/m CMOS , 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.

[13]  S. Solmi,et al.  Equilibrium Carrier Density and Solubility of Antimony in Silicon , 1989 .

[14]  S. Solmi,et al.  Experimental investigation and simulation of Sb diffusion in Si , 1992 .

[15]  C. Fiegna,et al.  Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junctions , 1993, Proceedings of IEEE International Electron Devices Meeting.

[16]  Kyoji Yamashita,et al.  A 0.05 /spl mu/m-CMOS with ultra shallow source/drain junctions fabricated by 5 keV ion implantation and rapid thermal annealing , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[17]  G. Sai-Halasz,et al.  Antimony and arsenic segregation at Si-SiO2interfaces , 1985, IEEE Electron Device Letters.

[18]  Hiroshi Iwai,et al.  Tunneling gate oxide approach to ultra-high current drive in small geometry MOSFETs , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[19]  R. H. Yan,et al.  High Performance 0.1 μm CMOS Devices , 1994 .