Research of Mixed-Voltage I/O ESD Protection Mechanism Implemented by Substrate-Triggered Technique

The substrate-triggered technique has an obvious improve on ESD level of the large-dimension NMOS devices. The substrate-triggered stacked-NMOS device that combines the substrate-triggered technique into the stacked-NMOS device is investigated. From the academic results, the substrate-triggered technique can increase ESD robustness of the stacked-NMOS device in the mixed-voltage I/O circuit. From the experimental results in a 0.35 μm CMOS process, HBM ESD level of the proposed ESD protection design by using stacked-NMOS with substrate-triggered technique can be improved up to ~60%. This has verified the effectiveness of the substrate-triggered design to improve ESD level of mixed-voltage I/O circuits.