A superscalar architecture to exploit instruction level parallelism

Abstract If a high-performance superscalar processor is to realise its full potential, the compiler must re-order or schedule the object code at compile time. This scheduling creates groups of adjacent instructions that are independent and which therefore can be issued and executed in parallel at run time. This paper provides an overview of the Hatfield Superscalar Architecture (HSA), a multipleinstruction-issue architecture developed at the University of Hertfordshire to support the development of high-performance instruction schedulers. The long-term objective of the HSA project is to develop the scheduling technology to realise an order of magnitude performance improvement over traditional RISC designs. The paper also presents results from the first HSA instruction scheduler that currently achieves a speedup of over three compared to a classic RISC processor.

[1]  Edward McLellan.  The Alpha AXP architecture and 21064 processor , 1993, IEEE Micro.

[2]  David W. Wall,et al.  Limits of instruction-level parallelism , 1991, ASPLOS IV.

[3]  G. B. Steven,et al.  iHARP: a multiple instruction issue processor , 1992 .

[4]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[5]  Alexandru Nicolau,et al.  Run-Time Disambiguation: Coping with Statically Unpredictable Dependencies , 1989, IEEE Trans. Computers.

[6]  Gordon B. Steven,et al.  Investigating the Limits of Fine-Grained Parallelism in a Statically Scheduled Superscalar Architecture , 1996, Euro-Par, Vol. II.

[7]  Yale N. Patt,et al.  Alternative implementations of two-level adaptive branch prediction , 1992, ISCA '92.

[8]  Scott A. Mahlke,et al.  Characterizing the impact of predicated execution on branch prediction , 1994, Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture.

[9]  Rod Adams,et al.  Addressing mechanisms for VLIW and superscalar processors , 1993, Microprocess. Microprogramming.

[10]  G. S. Rao,et al.  6th annual symposium on computer architecture , 1979 .

[11]  Donald B. Alpert,et al.  Architecture of the Pentium microprocessor , 1993, IEEE Micro.

[12]  Stephen B. Furber,et al.  VLSI Risc Architecture and Organization , 1989 .

[13]  Monica S. Lam,et al.  Limits of control flow on parallelism , 1992, ISCA '92.

[14]  Gordon B. Steven,et al.  HARP: A parallel pipelined RISC processor , 1989, Microprocess. Microsystems.

[15]  Gordon B. Steven,et al.  Instruction scheduling for a superscalar architecture , 1996, Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies.

[16]  G. B. Steven,et al.  Using a resource limited instruction scheduler to evaluate the iHARP processor , 1995 .

[17]  Edward S. Davidson,et al.  Highly concurrent scalar processing , 1986, ISCA 1986.

[18]  S. Peter Song,et al.  The PowerPC 604 RISC microprocessor. , 1994, IEEE Micro.

[19]  Gordon B. Steven,et al.  An explicitly declared delayed-branch mechanism for a superscalar architecture , 1994, Microprocess. Microprogramming.

[20]  Mike Johnson,et al.  Superscalar microprocessor design , 1991, Prentice Hall series in innovative technology.

[21]  Andrew R. Pleszkun,et al.  Implementing Precise Interrupts in Pipelined Processors , 1988, IEEE Trans. Computers.

[22]  Michael Shebanow,et al.  Single instruction stream parallelism is greater than two , 1991, ISCA '91.

[23]  Steven E. Shladover.  Research and development needs for advanced vehicle control systems , 1993, IEEE Micro.

[24]  Kemal Ebcioglu,et al.  An efficient resource-constrained global scheduling technique for superscalar and VLIW processors , 1992, MICRO 1992.

[25]  B. Ramakrishna Rau,et al.  The Cydra 5 departmental supercomputer: design philosophies, decisions, and trade-offs , 1989, Computer.

[26]  Siamak Arya,et al.  An architecture for high instruction level parallelism , 1995, Proceedings of the Twenty-Eighth Annual Hawaii International Conference on System Sciences.

[27]  Gordon B. Steven,et al.  ALU design and processor branch architecture , 1993, Microprocess. Microprogramming.