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[1] Bruce Schneier,et al. Side Channel Cryptanalysis of Product Ciphers , 1998, J. Comput. Secur..
[2] Carsten Willems,et al. Practical Timing Side Channel Attacks against Kernel Space ASLR , 2013, 2013 IEEE Symposium on Security and Privacy.
[3] Amir Rahmati,et al. Probable cause: The deanonymizing effects of approximate DRAM , 2015, 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA).
[4] Zaid Al-Ars. DRAM fault analysis and test generation , 2005 .
[5] Stefan Mangard,et al. Cache Template Attacks: Automating Attacks on Inclusive Last-Level Caches , 2015, USENIX Security Symposium.
[6] Barbara P. Aichinger,et al. DDR memory errors caused by Row Hammer , 2015, 2015 IEEE High Performance Extreme Computing Conference (HPEC).
[7] Stefan Mangard,et al. Reverse Engineering Intel DRAM Addressing and Exploitation , 2015, ArXiv.
[8] Aamer Jaleel,et al. Adaptive insertion policies for high performance caching , 2007, ISCA '07.
[9] Angelos D. Keromytis,et al. The Spy in the Sandbox: Practical Cache Attacks in JavaScript and their Implications , 2015, CCS.
[10] Gernot Heiser,et al. Mapping the Intel Last-Level Cache , 2015, IACR Cryptol. ePrint Arch..
[11] Rei-Fu Huang,et al. Alternate hammering test for application-specific DRAMs and an industrial case study , 2012, DAC Design Automation Conference 2012.
[12] Gernot Heiser,et al. Last-Level Cache Side-Channel Attacks are Practical , 2015, 2015 IEEE Symposium on Security and Privacy.
[13] Klaus Wagner,et al. Flush+Flush: A Stealthier Last-Level Cache Attack , 2015, ArXiv.
[14] Daniel J. Bernstein,et al. Cache-timing attacks on AES , 2005 .
[15] Varghese George,et al. Power management of the third generation intel core micro architecture formerly codenamed ivy bridge , 2012, 2012 IEEE Hot Chips 24 Symposium (HCS).
[16] Gorka Irazoqui Apecechea,et al. S$A: A Shared Cache Attack That Works across Cores and Defies VM Sandboxing -- and Its Application to AES , 2015, 2015 IEEE Symposium on Security and Privacy.
[17] Chris Fallin,et al. Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors , 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).
[18] Nicolas Le Scouarnec,et al. Reverse Engineering Intel Last-Level Cache Complex Addressing Using Performance Counters , 2015, RAID.
[19] Eli Biham,et al. Differential Fault Analysis of Secret Key Cryptosystems , 1997, CRYPTO.
[20] Klaus Wagner,et al. Flush+Flush: A Fast and Stealthy Cache Attack , 2015, DIMVA.
[21] Yuval Yarom,et al. FLUSH+RELOAD: A High Resolution, Low Noise, L3 Cache Side-Channel Attack , 2014, USENIX Security Symposium.
[22] Paul C. Kocher,et al. Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems , 1996, CRYPTO.
[23] Kyungbae Park,et al. Active-precharge hammering on a row induced failure in DDR3 SDRAMs under 3× nm technology , 2014, 2014 IEEE International Integrated Reliability Workshop Final Report (IIRW).
[24] Bruce Schneier,et al. Side channel cryptanalysis of product ciphers , 2000 .
[25] Aurélien Francillon,et al. C5: Cross-Cores Cache Covert Channel , 2015, DIMVA.
[26] Gorka Irazoqui Apecechea,et al. Seriously, get off my cloud! Cross-VM RSA Key Recovery in a Public Cloud , 2015, IACR Cryptol. ePrint Arch..
[27] Thomas R. Gross,et al. CAIN: Silently Breaking ASLR in the Cloud , 2015, WOOT.
[28] Stephan Krenn,et al. Cache Games -- Bringing Access-Based Cache Attacks on AES to Practice , 2011, 2011 IEEE Symposium on Security and Privacy.
[29] Adi Shamir,et al. Cache Attacks and Countermeasures: The Case of AES , 2006, CT-RSA.
[30] Colin Percival. CACHE MISSING FOR FUN AND PROFIT , 2005 .
[31] Mathias Payer,et al. HexPADS: A Platform to Detect "Stealth" Attacks , 2016, ESSoS.
[32] Reetuparna Das,et al. ANVIL: Software-Based Protection Against Next-Generation Rowhammer Attacks , 2016, ASPLOS.
[33] Stefan Mangard,et al. ARMageddon: Last-Level Cache Attacks on Mobile Devices , 2015, ArXiv.
[34] Richard J. Lipton,et al. On the Importance of Checking Cryptographic Protocols for Faults (Extended Abstract) , 1997, EUROCRYPT.
[35] Stefan Mangard,et al. Practical Memory Deduplication Attacks in Sandboxed Javascript , 2015, ESORICS.
[36] Hiroshi Miyauchi,et al. Cryptanalysis of DES Implemented on Computers with Cache , 2003, CHES.
[37] Dan Page,et al. Theoretical Use of Cache Memory as a Cryptanalytic Side-Channel , 2002, IACR Cryptol. ePrint Arch..
[38] Dae-Hyun Kim,et al. Architectural Support for Mitigating Row Hammering in DRAM Memories , 2015, IEEE Computer Architecture Letters.