Lifetime Calculation Using a Stochastic Reliability Simulator for Analog ICs

Due to the impact of technology downscaling into the nanometer scale, designers have to take into account not only the degradation of circuit performances due to time-zero variability but also the degradation due to time-dependent variability. To evaluate their impact in the circuit performances, a critical metric is the time-dependent yield, the percentage of circuit samples of a particular design that operates correctly with respect to a set of performance constraints, a metric that, due to the presence of time-dependent variability, changes over time. The lifetime of the circuit, or the time the circuit is working above a pre-defined yield threshold can be calculated using the time-dependent yield. These are crucial metrics, even fundamental in many applications. This work proposes a new efficient simulation methodology that can provide an accurate calculation of time-dependent yield and lifetime using a stochastic reliability simulator for analog circuits while keeping CPU times low.

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