A software framework for pipelined arithmetic algorithms in field programmable gate arrays

Abstract Pipelined algorithms implemented in field programmable gate arrays are extensively used for hardware triggers in the modern experimental high energy physics field and the complexity of such algorithms increases rapidly. For development of such hardware triggers, algorithms are developed in C++ , ported to hardware description language for synthesizing firmware, and then ported back to C++ for simulating the firmware response down to the single bit level. We present a C++ software framework which automatically simulates and generates hardware description language code for pipelined arithmetic algorithms.

[1]  Jinyuan Wu,et al.  FPGA Curved Track Fitters and a Multiplierless Fitter Scheme , 2008, IEEE Transactions on Nuclear Science.

[2]  I. R. Arcas,et al.  The ATLAS Level-1 trigger timing setup , 2005, 14th IEEE-NPSS Real Time Conference, 2005..

[3]  K. Arinstein,et al.  Belle II Technical Design Report , 2010, 1011.0352.

[4]  E. Won,et al.  A hardware implementation of artificial neural networks using field programmable gate arrays , 2007, physics/0703041.

[5]  Toshihiro Mimashi,et al.  Accelerator design at SuperKEKB , 2013 .

[8]  P. Klabbers,et al.  Operation and Performance of the CMS Level-1 Trigger during 7 TeV Collisions , 2012 .

[9]  Peter M. Athanas,et al.  Quantitative analysis of floating point arithmetic on FPGA based custom computing machines , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[10]  R. Itoh,et al.  Data Flow and High Level Trigger of Belle II DAQ System , 2013, IEEE Transactions on Nuclear Science.

[11]  C.-H Wang,et al.  The status of high-speed trigger multiplexer module with aurora protocol implemented on Arria II FPGA for the Belle II Cylindrical Drift Chamber detector , 2013, 2013 IEEE Nuclear Science Symposium and Medical Imaging Conference (2013 NSS/MIC).

[12]  Eunil Won,et al.  Level 1 Trigger System for the Belle II Experiment , 2010, IEEE Transactions on Nuclear Science.

[13]  J. Chaves.  Implementation of FPGA-based level-1 tracking at CMS for the HL-LHC , 2014 .

[14]  Zhiru Zhang,et al.  FPGA-Based Real-Time Charged Particle Trajectory Reconstruction at the Large Hadron Collider , 2017, 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

[15]  D. Gigi,et al.  The data-acquisition system of the CMS experiment at the LHC , 2011 .

[16]  E. Won,et al.  Three-dimensional fast tracker for the central drift chamber based level-1 trigger system in the Belle II experiment , 2017 .

[17]  K. Perez.  Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment , 2014 .

[18]  S Ballestrero,et al.  The ATLAS Data Acquisition and High Level Trigger system , 2006 .

[19]  Scott McMillan,et al.  A re-evaluation of the practicality of floating-point operations on FPGAs , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).