Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers

Two equalizer filter topologies and a merged equalizer/CDR circuit are described that operate at 10 Gb/s in 0.13-mum CMOS technology. Using techniques such as reverse scaling, passive peaking networks, and dual- and triple-loop adaptation, the prototypes adapt to FR4 trace lengths up to 24 inches. The equalizer/CDR circuit retimes the data with a bit error rate of 10-13 while consuming 133 mW from a 1.6-V supply.

[1]  J.D.H. Alexander.  Clock recovery from random binary signals , 1975 .

[2]  Deog-Kyoon Jeong,et al.  A 0.18-/spl mu/m CMOS 3.5-gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method , 2004 .

[3]  J. A. Mataya,et al.  IF Amplifier using C/SUB c/ compensated transistors , 1968 .

[4]  E. Sackinger,et al.  A 3-GHz 32-dB CMOS limiting amplifier for SONET OC-48 receivers , 2000, IEEE Journal of Solid-State Circuits.

[5]  Renuka P. Jindal.  Gigahertz-band high-gain low-noise AGC amplifiers in fine-line NMOS , 1987 .

[6]  Vladimir Stojanovic,et al.  Modeling and analysis of high-speed links , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[7]  J. Stonick,et al.  A multigigabit backplane transceiver core in 0.13-/spl mu/m CMOS with a power-efficient equalization architecture , 2005, IEEE Journal of Solid-State Circuits.

[8]  A.J. Baker.  An adaptive cable equalizer for serial digital video rates to 400 Mb/s , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[9]  J. A. Mataya,et al.  IF amplifier using Cc compensated transistors , 1968 .

[10]  B. Razavi,et al.  10-Gb/s limiting amplifier and laser/modulator driver in 0.18-μm CMOS technology , 2003, IEEE J. Solid State Circuits.

[11]  Michael M. Green,et al.  A BiCMOS 10Gb/s adaptive cable equalizer , 2004 .

[12]  Chu-Sun Yen,et al.  Time-domain skin-effect model for transient analysis of lossy transmission lines , 1982, Proceedings of the IEEE.

[13]  W. Walker,et al.  A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-/spl mu/m CMOS , 2005, IEEE Journal of Solid-State Circuits.

[14]  Behzad Razavi,et al.  Design techniques for low-voltage high-speed digital bipolar circuits , 1994 .

[15]  M.H. Shakiba.  A 2.5 Gb/s adaptive cable equalizer , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[16]  V. Gupta,et al.  A 6.25-Gb/s binary transceiver in 0.13-/spl mu/m CMOS for serial data transmission across high loss legacy backplane channels , 2005, IEEE Journal of Solid-State Circuits.

[17]  B.L. Ji,et al.  A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization , 2005, IEEE Journal of Solid-State Circuits.

[18]  Jri Lee,et al.  A 10Gb/s CMOS adaptive equalizer for backplane applications , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[19]  B. Razavi,et al.  A 10-Gb/s CMOS Merged Adaptive Equalizer/CDR Circuit for Serial-Link Receivers , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..