Error correction circuits for bio-implantable electronics

Methods are reviewed for achieving high data rates in bio-implantable devices. Particular attention is given to cortical stimulator arrays for restoring vision. Error-correction codes (ECC) are shown to be essential to obtain reliable operation in next-generation high-rate implants. A survey of reported ECC implementations is presented, and power-vs-performance tradeoffs are revealed after re-scaling to remove differences in technology and clock speed. Recommendations are offered for realizing high-rate ECC circuits within the tight power constraints of implantable device applications.

[1]  C. Plett,et al.  A 0.18-$muhbox m$CMOS Analog Min-Sum Iterative Decoder for a (32,8) Low-Density Parity-Check (LDPC) Code , 2006, IEEE Journal of Solid-State Circuits.

[2]  Sameer R. Sonkusale,et al.  Fully Digital BPSK Demodulator and Multilevel LSK Back Telemetry for Biomedical Implant Transceivers , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[3]  A. Demosthenous,et al.  A 100Mb/s, 2.8V CMOS current-mode analogue Viterbi decoder , 2001, Proceedings of the 27th European Solid-State Circuits Conference.

[4]  Robert G. Gallager,et al.  Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.

[5]  Chi-Ying Tsui,et al.  A low power layered decoding architecture for LDPC decoder implementation for IEEE 802.11n LDPC codes , 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

[6]  Cameron T. Charles.  An implantable I-UWB transceiver architecture with power carrier synchronization , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[7]  Joachim Hagenauer,et al.  WA 21.5 An Analog 0.25∝m BiCMOS Tailbiting MAP Decoder , 2000 .

[8]  Andreas Demosthenous,et al.  A 100 Mb/s, 2.8 V CMOS current-mode analogue Viterbi decoder (invited paper) , 2002 .

[9]  A. Glavieux,et al.  Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1 , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.

[10]  Norbert Wehn,et al.  A 150Mbit/s 3GPP LTE Turbo code decoder , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[11]  Chih-Hung Lin,et al.  Low-power design of variable block-size LDPC decoder using nanometer technology , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[12]  Vincent C. Gaudet,et al.  Decoder IC with a Configurable Interleaver , 2003 .

[13]  Christophe Jégo,et al.  A highly parallel Turbo Product Code decoder without interleaving resource , 2008, 2008 IEEE Workshop on Signal Processing Systems.

[14]  T Stieglitz,et al.  Implantable microsystems for monitoring and neural rehabilitation, part I. , 2001, Medical device technology.

[15]  Mohammad M. Mansour,et al.  A 640-Mb/s 2048-bit programmable LDPC decoder chip , 2006, IEEE Journal of Solid-State Circuits.

[16]  M. Sawan,et al.  Wireless Smart Implants Dedicated to Multichannel Monitoring and Microstimulation , 2005, The IEEE/ACS International Conference on Pervasive Services.

[17]  P.G. Gulak,et al.  A 13.3Mb/s 0.35/spl mu/m CMOS analog turbo decoder IC with a configurable interleaver , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[18]  Indrajit Chakrabarti,et al.  An improved low-power high-throughput log-MAP turbo decoder , 2010, IEEE Transactions on Consumer Electronics.

[19]  Frank R. Kschischang,et al.  Power Reduction Techniques for LDPC Decoders , 2008, IEEE Journal of Solid-State Circuits.

[20]  Cheng-Chi Wong,et al.  A multiple code-rate turbo decoder based on reciprocal dual trellis architecture , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[21]  Joseph R. Cavallaro,et al.  A low-power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standards , 2008, 2008 IEEE International SOC Conference.

[22]  Bruce F. Cockburn,et al.  A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[23]  Joseph R. Cavallaro,et al.  Scalable and low power LDPC decoder design using high level algorithmic synthesis , 2009, 2009 IEEE International SOC Conference (SOCC).

[24]  Scott A. Mahlke,et al.  Design and Implementation of Turbo Decoders for Software Defined Radio , 2006, 2006 IEEE Workshop on Signal Processing Systems Design and Implementation.

[25]  An-Yeu Wu,et al.  Dual-mode convolutional/SOVA based turbo code decoder VLSI design for wireless communication systems , 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

[26]  Robert H. Dennard,et al.  A perspective on today’s scaling challenges and possible future directions , 2007 .

[27]  Wai-Chi Fang,et al.  VLSI design of turbo decoder for integrated communication system-on-chip applications , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[28]  Gwan S. Choi,et al.  Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels , 2009, 2009 22nd International Conference on VLSI Design.

[29]  H. Loeliger,et al.  Probability propagation and decoding in analog VLSI , 1998, Proceedings. 1998 IEEE International Symposium on Information Theory (Cat. No.98CH36252).

[30]  Maysam Ghovanloo,et al.  A wideband frequency-shift keying wireless link for inductively powered biomedical implants , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[31]  Maysam Ghovanloo,et al.  A wideband power-efficient inductive wireless link for implantable microelectronic devices using multiple carriers , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[32]  Nhan Nguyen,et al.  Low-voltage CMOS circuits for analog iterative decoders , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[33]  R.R. Harrison,et al.  A Low-Power Integrated Circuit for a Wireless 100-Electrode Neural Recording System , 2006, IEEE Journal of Solid-State Circuits.

[34]  Sameer R. Sonkusale,et al.  A Novel BPSK Demodulator for Biological Implants , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[35]  Radford M. Neal,et al.  Near Shannon limit performance of low density parity check codes , 1996 .

[36]  R Bashirullah,et al.  Wireless Implants , 2010, IEEE Microwave Magazine.

[37]  Joachim Hagenauer,et al.  The analog decoder , 1998, Proceedings. 1998 IEEE International Symposium on Information Theory (Cat. No.98CH36252).

[38]  Vincent C. Gaudet,et al.  Scaling of analog LDPC decoders in sub-100 nm CMOS processes , 2010, Integr..

[39]  Zhongfeng Wang,et al.  Low power decoder design for QC-LDPC codes , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[40]  Chia-Chun Tsai,et al.  A new low-power turbo decoder using HDA-DHDD stopping iteration , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[41]  C.T. Charles.  Wireless Data Links for Biomedical Implants: Current Research and Future Directions , 2007, 2007 IEEE Biomedical Circuits and Systems Conference.

[42]  Rahul Khanna,et al.  A 90 nm-CMOS, 500 Mbps, 3–5 GHz Fully-Integrated IR-UWB Transceiver With Multipath Equalization Using Pulse Injection-Locking for Receiver Phase Synchronization , 2011, IEEE Journal of Solid-State Circuits.

[43]  Andreas Demosthenous,et al.  A CMOS Hard-Decision Analog Convolutional Decoder Employing the MFDA for Low-Power Applications , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[44]  Maysam Ghovanloo,et al.  A Wide-Band Power-Efficient Inductive Wireless Link for Implantable Microelectronic Devices Using Multiple Carriers , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[45]  Maysam Ghovanloo,et al.  Wideband Near-Field Data Transmission Using Pulse Harmonic Modulation , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[46]  Richard A. Normann,et al.  Simulation of a phosphene-based visual field: Visual acuity in a pixelized vision system , 2006, Annals of Biomedical Engineering.

[47]  A. Neviani,et al.  A 0.35-/spl mu/m CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code , 2005, IEEE Journal of Solid-State Circuits.

[48]  Daryl R. Kipke,et al.  Wireless implantable microsystems: high-density electronic interfaces to the nervous system , 2004, Proceedings of the IEEE.

[49]  Thomas Stieglitz,et al.  Implantable microsystems for monitoring and neural rehabilitation, Part II. , 2001, Medical device technology.

[50]  R.R. Harrison,et al.  CMOS analog MAP decoder for (8,4) Hamming code , 2004, IEEE Journal of Solid-State Circuits.

[51]  Yi Luo,et al.  125Mbps ultra-wideband system evaluation for cortical implant devices , 2012, 2012 Annual International Conference of the IEEE Engineering in Medicine and Biology Society.

[52]  Luca Fanucci,et al.  A parallel VLSI architecture for 1-Gb/s, 2048-b, rate-1/2 turbo Gallager code decoder , 2004 .