On Multi-Cycle False Paths in Sequential Circuits

In this paper we analyze the problem of multi-cycle false paths in sequential circuits and their impact on circuit performance. We present a study on the identification and removal of multi-cycle false paths from sequential machines specified at the functional and behavioral levels and show that multi-cycle false paths are not a property of the gate-level implementation but a property of the behavior of the machine and its state encoding. Based on behavioral level analysis, we derive the necessary and sufficient condition for the encoding of an FSM to obtain a false path free implementation and present a systematic encoding methodology to obtain a sequential false-path-free circuit. The experimental results show significant clock cycle reduction in sequential circuits encoded with this method.

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