论文信息 - Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation

Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation

In many embedded systems for video surveillance distinctive features are used for the detection of objects. In this contribution a real-time FPGA implementation of a feature detector, namely the SUSAN algorithm is described. As the original SUSAN algorithm performs poorly on non-synthetic images a significant quality improvement of this algorithm is presented. The hardware accelerator outperforms a comparable software version running on an Intel Core2Duo E8400 core at 3.00GHz and delivers almost the same execution time compared to an implementation of the Harris corner detector running on an Nvidia GeForce 8800 GTX GPU.

Walter Stechele | Robert Huitl | Christopher Claus | Joachim Rausch

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