A 15-ns CMOS 64K RAM

The RAM was built using a technology with self-aligned TiSi/SUB 2/, single-level metal, an average minimum feature size of 1.35 /spl mu/m, and a minimum effective channel length of 1.1 /spl mu/m. An access of 10 ns is possible with the word line stitched on a second level of metal and some minor redesign. High speed is achieved through innovative circuits and design concepts. Novel CMOS circuits include a sense-amp set signal generator, a row decoder, and an input circuit. A layout-rule-independent graphics tool, which was used for the artwork design, is discussed.

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