Configurable spare processors: a new approach to system level fault-tolerance

In this paper, we have developed a methodology for behavioral synthesis of an important class of reconfigurable data path designs called configurable spare processors. Traditionally, a processor failure has been tolerated by dedicating a spare for the processor. However, this has a significant area overhead. In contrast, we present a new technique wherein several processors share one or more configurable spare processors. A configurable spare efficiently implements any of k applications and can be configured to substitute for a faulty processor implementing one of these k applications. In this paper, we address three important techniques targeting configurable spare processor synthesis. Firstly, we address application bundling wherein n application control-data flow graphs (CDFGs) are bundled into at most m groups such that the sum of the areas of the corresponding implementations is minimized. All throughput and fault-tolerance constraints for all applications are satisfied. The area overhead of each of the application bundles is further optimised by retiming the applications within a bundle by considering its effects on the remaining applications in the bundle. Finally, each application bundle is synthesized into a configurable spare processor. The effectiveness of all approaches, algorithms, and software implementations is demonstrated on a number of real-life examples. The validation of all presented examples is complete in a sense that we conducted functional simulation to complete layout implementations.

[1]  Ramesh Karri,et al.  Optimal self-recovering microarchitecture synthesis , 1993, FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing.

[2]  Alice C. Parker,et al.  The high-level synthesis of digital systems , 1990, Proc. IEEE.

[3]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[4]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[5]  Miodrag Potkonjak,et al.  Fast prototyping of datapath-intensive architectures , 1991, IEEE Design & Test of Computers.

[6]  Daniel D. Gajski,et al.  High ― Level Synthesis: Introduction to Chip and System Design , 1992 .

[7]  Ramesh Karri,et al.  Automatic Synthesis of Self-Recovering VLSI Systems , 1996, IEEE Trans. Computers.

[8]  Douglas M. Blough,et al.  Optimal recovery point insertion for high-level synthesis of recoverable microarchitectures , 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[9]  Ramesh Karri,et al.  Phantom redundancy: a high-level synthesis approach for manufacturability , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[10]  Minh N. Do,et al.  Youn-Long Steve Lin , 1992 .

[11]  W.R. Moore,et al.  A review of fault-tolerant techniques for the enhancement of integrated circuit yield , 1986, Proceedings of the IEEE.

[12]  Ramesh Karri,et al.  Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[13]  Miodrag Potkonjak,et al.  High level synthesis techniques for efficient built-in-self-repair , 1993, Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

[14]  Edward A. Lee,et al.  Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing , 1989, IEEE Transactions on Computers.