CMOS SRAM functional test with quiescent write supply current

A large quiescent supply current of mA order flows when a data is written in a CMOS SRAM IC. In this paper an SRAM test method is proposed which is based on the supply current and whose purpose is to detect logically faulty IC's. The method is evaluated by some experiments. In the experiments, about 80% of faulty CMOS SRAM IC's are detected. Also it is shown that the total test time can be reduced if the method is used in the pretest stage of a functional test.

[1]  Ad J. van de Goor,et al.  An overview of deterministic functional RAM chip testing , 1990, CSUR.

[2]  Wojciech Maly,et al.  Test generation for current testing , 1989, [1989] Proceedings of the 1st European Test Conference.

[3]  Masaki Hashizume,et al.  CMOS SRAM test based on quiescent supply current in write operation , 1995, Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing.

[4]  Wojciech Maly,et al.  Test generation for current testing (CMOS ICs) , 1990, IEEE Design & Test of Computers.

[5]  Bas Verhelst,et al.  Functional and I/sub DDQ/ testing on a static RAM , 1990, Proceedings. International Test Conference 1990.

[6]  Ad J. van de Goor,et al.  Using March Tests to Test SRAMs , 1993, IEEE Des. Test Comput..

[7]  Charles F. Hawkins,et al.  Electrical Characteristics and Testing Considerations for Gate Oxide Shorts in CMOS ICs , 1985, ITC.

[8]  Hiroshi Yokoyama,et al.  A current testing for CMOS static RAMs , 1993, Records of the 1993 IEEE International Workshop on Memory Testing.