An Architecture Study of Scalable Optical-Flow Processor for Real-Time Video Segmentation

1. Abstract This paper proposes optical-flow processor architecture for real-time video segmentation. The architecture embodies the hierarchical optical-flow estimation (HOE) algorithm, and achieves scalability in terms of pixel rate and accuracy. In order to reduce a hardware resource cost of the processor, we introduce a common element (CE) that carries out all calculations necessary to optical-flow derivation. For area efficiency, a 2-port DRAM compatible with a logic process is adopted. When one CE is implemented on a chip in a 90-nm process technology, the processor performs 34 GOPS at a clock frequency of 189 MHz, and can handle a CIF-30 image sequence. The core size and power are estimated at 6.02 × 5.33 mm 2 and 0.5 W, respectively.