A Survey : System-ona-Chip Design and Verification

In this technical report, we survey the state-of-the-art of the design and verification techniques and methodologies the System on-a-Chip (SoC). The advancement in the hardware area made it possible the integration of a complete yet complex system on a single chip. Over 10 million gates, integrated together and running a real time optimized software red crossed classical design techniques. Traditional Regiter Transfer level (RTL) will serve as an assembler language for the new design languages or so called system level languages. A challenge facing the SoC designers is to decide which system level language we have to use and how the verification task will be accomplished. This report presents the main proposals in defining a system level language and discusses the eventual verification techniques that can be used.

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