The AIGER And-Inverter Graph (AIG) Format Version 20070427

This report describes the AIG file format as used by the AIGER library. The purpose of this report is not only to motivate and document the format, but also to allow independent implementations of writers and readers by giving precise and unambiguous definitions. Acknowledgements The format went through various incarnations even before real code became available. In particular the following colleagues gave invaluable feedback on earlier drafts.

[1]  Robert K. Brayton,et al.  DAG-aware AIG rewriting: a fresh look at combinational logic synthesis , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[2]  Parosh Aziz Abdulla,et al.  Symbolic Reachability Analysis Based on SAT-Solvers , 2000, TACAS.

[3]  Henrik Reif Andersen,et al.  Boolean Expression Diagrams , 2002, Inf. Comput..

[4]  Per Bjesse,et al.  DAG-aware circuit compression for formal verification , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[5]  Malay K. Ganai,et al.  Circuit-based Boolean reasoning , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[6]  Malay K. Ganai,et al.  Robust Boolean reasoning for equivalence checking and functional property verification , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..