A hardware overview of SX-6 and SX-7 supercomputer

NEC has been developing vector supercomputers since 1983 to meet the growing demand for high performance computing (HPC), especially in scientific and engineering fields. SX-6 and SX-7 were developed to meet the limitless requirement for computation. A single-chip vector CPU including eight vector pipelines and a scalar unit was developed for SX-6 and SX-7. Vector pipeline and scalar unit design will be discussed. To achieve high performance and realize high sustained performance, a combination of vector type processor and high bandwidth architecture was exploited. For more performance a multi-node system was developed. A single-stage crossbar switch was developed to achieve high bandwidth and to minimize the delay because of contention. As a result, theoretical peak performance of 64GFLOPS was achieved for 8 CPU, and up to 8TFLOPS for a multimode system. To develop the low cost and high-performance supercomputer SX-6, all functions of the vector CPU are integrated on a single die. This was achieved by 0.15μm Cu interconnection CMOS technology.