The Seamless Computation Model for Efficient Use of Parallel Multiprocessors

Seamless is a model of parallel computation with three primary characteristics and goals: a locality-based data movement programming paradigm, latency-tolerance, and the exploitation of current RISC CPU technology to address fine-grain parallelism without multithreading. These aspects form the underlying framework to which we are designing both a programming language interface and a hardware implementation of the model. This paper describes the essential characteristics of this model, motivates the choice of its elements, and provides a flavor for both language-level support and machine-level implementation.

[1]  A. Gupta,et al.  Exploring the benefits of multiple hardware contexts in a multiprocessor architecture: preliminary results , 1989, ISCA '89.

[2]  Robert H. Halstead,et al.  MASA: a multithreaded processor architecture for parallel symbolic computing , 1988, [1988] The 15th Annual International Symposium on Computer Architecture. Conference Proceedings.

[3]  David E. Culler,et al.  Analysis of multithreaded architectures for parallel computing , 1990, SPAA '90.

[4]  James Arthur Kohl,et al.  A Tool to Aid in the Design, Implementation, and Understanding of Matrix Algorithms for Parallel Processors , 1990, J. Parallel Distributed Comput..

[5]  Thomas L. Casavant,et al.  Seamless - a latency-tolerant RISC-based multiprocessor architecture , 1992, ISCA.

[6]  Burton J. Smith,et al.  The Horizon supercomputing system: architecture and software , 1988, Proceedings. SUPERCOMPUTING '88.

[7]  James E. Rumbaugh,et al.  A Data Flow Multiprocessor , 1977, IEEE Transactions on Computers.

[8]  Robert H. Thomas,et al.  Performance Measurements on a 128-Node Butterfly Parallel Processor , 1985, International Conference on Parallel Processing.

[9]  Charles L. Seitz,et al.  Multicomputers: message-passing concurrent computers , 1988, Computer.

[10]  Anant Agarwal,et al.  APRIL: a processor architecture for multiprocessing , 1990, ISCA '90.

[11]  R. S. Nikhil.  Can dataflow subsume von Neumann computing? , 1989, ISCA '89.

[12]  Jack B. Dennis,et al.  Data Flow Supercomputers , 1980, Computer.

[13]  Thomas L. Casavant,et al.  A Preliminary Performance Evaluation of the Seamless Parallel Processing System Architecture , 1992, ICPP.

[14]  Allan Porterfield,et al.  The Tera computer system , 1990, ICS '90.

[15]  R. Arlauskas.  iPSC/2 system: a second generation hypercube , 1988, C3P.