The effects of scaling on the performance of small-signal MOS amplifiers

Abstract The impact of scaling of the CMOS technology on the performance of small-signal MOS amplifiers is evaluated by analytical models and physics-based device simulation. The limitations set by non-ideal scaling of the electrical characteristics of the MOSFET and their implications on the trade-off between power dissipation and performance are analyzed and discussed. The results reported in this paper give indications about the improvements and limitations that may be expected as the technology is scaled below 0.1 μm and provide indications regarding technology options (e.g. bulk vs. SOI MOSFETs) and different possible approaches for scaling the bias current as CMOS miniaturization proceeds.

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