Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core

Fault tolerance is an important feature for the system LSIs used in reliability-critical systems. Although redundancy techniques are generally used to provide fault tolerance, these techniques have significantly hardware costs. However, FPGAs can easily provide high reliability due to their reconfiguration ability. Even if faults occur, the implemented circuit can perform correctly by reconfiguring to a fault-free region of the FPGA. In this paper, we examine an FPGA-IP core loaded in SoC and introduce a fault-tolerant technology based on fault detection and recovery as a CAD-level approach. To detect fault position, we add a route to the manufacturing test method proposed in earlier research and identify fault areas. Furthermore, we perform fault recovery at the logic tile and multiplexer levels using reconfiguration. The evaluation results for the FPGA-IP core loaded in the system LSI demonstrate that it was able to completely identify and avoid fault areas relative to the faults in the routing area. key words: fault tolerant, fault recovery, FPGA-IP

[1]  Kenneth B. Kent,et al.  VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling , 2011, TRETS.

[2]  Dionisios N. Pnevmatikatos,et al.  A novel SRAM-based FPGA architecture for efficient TMR fault tolerance support , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[3]  Hideo Ito,et al.  Defect and fault tolerance SRAM-based FPGAs by shifting the confoguration data , 2000 .

[4]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[5]  Andrew M. Tyrrell,et al.  The yield enhancement of field-programmable gate arrays , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[6]  Russell Tessier,et al.  Tolerating operational faults in cluster-based FPGAs , 2000, FPGA '00.

[7]  Marco D. Santambrogio,et al.  TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs , 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

[8]  Guy Lemieux,et al.  Analytical Framework for Switch Block Design , 2002, FPL.

[9]  Peter Y. K. Cheung,et al.  Fault tolerant methods for reliability in FPGAs , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[10]  Luigi Carro,et al.  Designing fault tolerant systems into SRAM-based FPGAs , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[11]  Narayanan Vijaykrishnan,et al.  FLAW: FPGA lifetime awareness , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[12]  Masahiro Iida,et al.  Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC , 2015, IEICE Trans. Inf. Syst..

[13]  John M. Emmert,et al.  A survey of fault tolerant methodologies for FPGAs , 2006, TODE.

[14]  Masahiro Koga,et al.  An Easily Testable Routing Architecture and Prototype Chip , 2012, IEICE Trans. Inf. Syst..

[15]  Russell Tessier,et al.  FPGA Architecture: Survey and Challenges , 2008, Found. Trends Electron. Des. Autom..

[16]  Masahiro Iida,et al.  A robust reconfigurable logic device based on less configuration memory logic cell , 2010, 2010 International Conference on Field-Programmable Technology.

[17]  Kazutoshi Kobayashi,et al.  NBTI-Induced Delay Degradation Analysis of FPGA Routing Structures , 2012, IPSJ Trans. Syst. LSI Des. Methodol..