Dynamic Compilation Framework with DVS for Reducing Energy Consumption in Embedded Processors

Dynamic voltage scaling (DVS) is an effective technique for reducing the energy consumption in embedded systems. There are several advantages using DVS technique into compiler framework. This paper present a framework for reducing energy consumption in embedded processors using the dynamic compiler collaborate with DVS technique. Two algorithms are implemented in this framework, and the framework is implemented using the Intel PIN systems and is deployed in a real hardware platform. Experimental results based on the software and hardware platform, show that significant energy saving are achieved while performance loss less than 5%.

[1]  Lizy K. John,et al.  Is Compiling for Performance — Compiling for Power? , 2001 .

[2]  Sharad Malik,et al.  Compile-time dynamic voltage scaling settings: opportunities and limits , 2003, PLDI '03.

[3]  Michael S. Hsiao,et al.  Compiler-directed dynamic voltage/frequency scheduling for energy reduction in microprocessors , 2001, ISLPED '01.

[4]  Bishop Brock,et al.  Dynamic Power Management for Embedded Systems , 2003 .

[5]  Mahmut T. Kandemir,et al.  Energy-conscious compilation based on voltage scaling , 2002, LCTES/SCOPES '02.

[6]  Frank Bellosa,et al.  Process cruise control: event-driven clock scaling for dynamic power management , 2002, CASES '02.

[7]  Krishna V. Palem,et al.  The emerging power crisis in embedded processors: what can a poor compiler do? , 2001, CASES '01.

[8]  Ulrich Kremer,et al.  The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction , 2003, PLDI '03.

[9]  Andrew Wolfe,et al.  Compilation techniques for low energy: an overview , 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.

[10]  Michael S. Hsiao,et al.  Compiler-Directed Dynamic Frequency and Voltage Scheduling , 2000, PACS.

[11]  Rastislav Bodík,et al.  Slack: maximizing performance under technological constraints , 2002, ISCA.

[12]  Margaret Martonosi,et al.  A dynamic compilation framework for controlling microprocessor energy and performance , 2005, 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05).

[13]  Diana Marculescu.  On the Use of Microarchitecture-Driven Dynamic Voltage Scaling , 2000 .

[14]  R. D. Valentine,et al.  The Intel Pentium M processor: Microarchitecture and performance , 2003 .

[15]  B. Brock,et al.  Dynamic power management for embedded systems [SOC design] , 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

[16]  M. Kandemir,et al.  Dynamic compilation for energy adaptation , 2002, ICCAD 2002.

[17]  黄江伟,et al.  The dynamic power management for embedded system with Poisson process , 2005 .

[18]  Michael Franz,et al.  Virtual-Machine Driven Dynamic Voltage Scaling , 2003 .

[19]  Sandhya Dwarkadas,et al.  Dynamic frequency and voltage control for a multiple clock domain microarchitecture , 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..

[20]  Massoud Pedram,et al.  Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Trade-Off Based on the Ratio of Off-Chip Access to On-Chip Computation Times , 2004, DATE.