Algorithms for switch level delay fault simulation

Delay test problems are well understood for gate level circuits. For certain logic families, delays depend on the charge stored at internal nodes. For such circuits, gate level models do not surface, A switch level simulator can be used for logic verification and stuck-at fault simulation. Toward making the delay fault simulation possible, this paper contributes three innovations to the switch-level technique: (1) Signals that remain steady over two consecutive vectors are identified using additional strength designations for charge and discharge paths; (2) Delay faults are propagated through MOS gates using articulation analyse's of the graph; and (3) A modified relaxation procedure determines the steady or non-steady status of signals at the same time it evaluates nodes. Experimental results demonstrate the validity of algorithms.

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