Test Compression Improvement with EDT Channel Sharing in SoC Designs

This paper proposes an innovative test compression technology for system-on-chip (SoC) designs to share scan input channels across multiple cores which use EDT [1] compression. A new DFT compression architecture is proposed to separate control and data channels such that the control channels can be individually accessible, whereas data channels can be shared among a group of cores. The paper illustrates the benefits of the proposed technology in both the enhancement of compression ratios and the flexibility of test compression planning in a core-based SoC design flow. Experimental results with a few large industrial SoCs demonstrate that using the proposed technology the compression can be improved up to 1.87X.

[1]  Prab Varma,et al.  A structured test re-use methodology for core-based system chips , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[2]  Bashir M. Al-Hashimi,et al.  A compression-driven test access mechanism design approach , 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

[3]  Nilanjan Mukherjee,et al.  X-Press Compactor for 1000x Reduction of Test Data , 2006, 2006 IEEE International Test Conference.

[4]  Nilanjan Mukherjee,et al.  Constraint driven pin mapping for concurrent SOC testing , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[5]  Nilanjan Mukherjee,et al.  EDT bandwidth management - Practical scenarios for large SoC designs , 2013, 2013 IEEE International Test Conference (ITC).

[6]  Hideo Fujiwara,et al.  System-on-chip test scheduling with reconfigurable core wrappers , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Nilanjan Mukherjee,et al.  Static pin mapping and SOC test scheduling for cores with multiple test sets , 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

[8]  Nicola Nicolici,et al.  Time-multiplexed test data decompression architecture for core-based SOCs with improved utilization of tester channels , 2005, European Test Symposium (ETS'05).

[9]  Jing Wang,et al.  Test access mechanism for multiple identical cores , 2008, 2009 International Test Conference.

[10]  Vivek Chickermane,et al.  SmartScan - Hierarchical test compression for pin-limited low power designs , 2013, 2013 IEEE International Test Conference (ITC).

[11]  Erik Jan Marinissen,et al.  Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip , 2002, J. Electron. Test..

[12]  Erik Jan Marinissen,et al.  A structured and scalable mechanism for test access to embedded reusable cores , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[13]  Erik Jan Marinissen,et al.  Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip , 2003, IEEE Trans. Computers.

[14]  Erik Jan Marinissen,et al.  Efficient test access mechanism optimization for system-on-chip , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Qiang Xu,et al.  Multi-frequency test access mechanism design for modular SOC testing , 2004, 13th Asian Test Symposium.

[16]  Irith Pomeranz,et al.  SOC test scheduling using simulated annealing , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[17]  Nilanjan Mukherjee,et al.  EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism , 2011, 2011 IEEE International Test Conference.

[18]  Nilanjan Mukherjee,et al.  Embedded deterministic test , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  Guoliang Li,et al.  Multi-level EDT to Reduce Scan Channels in SoC Designs , 2012, 2012 IEEE 21st Asian Test Symposium.

[20]  Krishnendu Chakrabarty,et al.  Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21]  Krishnendu Chakrabarty,et al.  A unified approach for SoC testing using test data compression and TAM optimization , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[22]  Sandeep Koranne.  Formulation of SOC Test Scheduling as a Network Transportation Problem , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[23]  Janak H. Patel,et al.  Enhancement of the Illinois scan architecture for use with multiple scan inputs , 2004, IEEE Computer Society Annual Symposium on VLSI.

[24]  Yervant Zorian,et al.  Wrapper design for embedded core test , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[25]  Nilanjan Mukherjee,et al.  EDT Bandwidth Management in SoC Designs , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[26]  Kuen-Jong Lee,et al.  Using a single input to support multiple scan chains , 1998, ICCAD '98.

[27]  Mark Mohammad Tehranipoor,et al.  Nine-coded compression technique for testing embedded cores in SoCs , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[28]  Nilanjan Mukherjee,et al.  Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm , 2002, Proceedings. International Test Conference.

[29]  Erik Jan Marinissen,et al.  Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling , 2009, IEEE Transactions on Computers.

[30]  Janusz Rajski,et al.  Bandwidth-aware test compression logic for SoC designs , 2012, 2012 17th IEEE European Test Symposium (ETS).

[31]  Erik Jan Marinissen,et al.  Effective and efficient test architecture design for SOCs , 2002, Proceedings. International Test Conference.

[32]  Nilanjan Mukherjee,et al.  Resource allocation and test scheduling for concurrent test of core-based SOC design , 2001, Proceedings 10th Asian Test Symposium.

[33]  Wu-Tung Cheng,et al.  A novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores , 2011, 2011 IEEE International Test Conference.

[34]  Krishnendu Chakrabarty,et al.  System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[35]  Kedarnath J. Balakrishnan,et al.  Test Cost Reduction for SoC Using a Combined Approach to Test Data Compression and Test Scheduling , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[36]  Erik G. Larsson,et al.  An Integrated Framework for the Design and Optimization of SOC Test Solutions , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[37]  Krishnendu Chakrabarty,et al.  Accepted for Publication in Ieee Transactions on Computer-aided Design of Integrated Circuits and Systems Test Scheduling for Core-based Systems Using Mixed-integer Linear Programming , 2000 .

[38]  Janak H. Patel,et al.  An incremental algorithm for test generation in Illinois scan architecture based designs , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[39]  Sudhakar M. Reddy,et al.  Core-clustering based SoC test scheduling optimization , 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

[40]  Krishnendu Chakrabarty,et al.  Test planning for modular testing of hierarchical SOCs , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.