On floorplans of planar graphs

Floor-planning is an early step in VLSI chip design where one decides relative location of functional entities of a circuit on a chip. A floor-plan is a rectangle partitioned into a set of disjoint rectilinear polygonal regions (called modules). A floor-plan F represents a plane graph G as follows: Each vertex of G corresponds to a module of F and two vertices are adjacent in G iff their corresponding modules share a common boundary. The quality of the final VLSI chip design heavily depends on the quality of the floor plan. Thus when constructing a floor plan of G, it is very desirable to use modules whose shapes are as simple as possible. If a module M is a union of k disjoint rectangles, M is called a k-rectangle module. There exist planar graphs whose floor plan must use nonrectangle modules. It was show in [26] that every planar graph G has a floor-plan using 1-, 2-, and 3-rectangle modules. It remains an open problem whether every planar graph G has a floor plan using only 1and 2-rectangle modules. In this paper, we settle this open question by presenting a simple linear time algorithm that constructs a floor-plan for G using only 1and 2-rectangle modules. A widely used heuristic algorithm for constructing floor plans (with 1and 2-rectangle modules) uses a “break-edge” method. We show that this heuristic algorithm does not work by presenting a graph whose floor plan must use 3-rectangle modules if the “break edge” algorithm is used.