A 1.3-cycle lock time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation for "clock on demand"

A 1.3-cycle lock-in time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation is proposed with an array structure of short-circuit-current-suppression interpolators. The circuits have been fabricated with a 0.25-/spl mu/m digital CMOS and operated in any condition where digital CMOS circuits operate. Measured results have achieved 1.3 clock cycle lock time and cycle-to-cycle jitter suppression characteristics. The circuits have been verified in 622-Mb/s clock and data recovery that satisfied the ITU-T G.958 jitter tolerance specification.

[1]  Marcel J. M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[2]  Masaki Sato,et al.  A jitter and data duty distortion tolerated PLL circuit for 156-Mbps burst-mode transmission , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[3]  B. Razavi.  PLL Design for a 500 MB/s Interface , 1996 .

[4]  Shimizu,et al.  A 10ps Jitter 2 Clock Cycle Lock Time Cmos Digital Clock Generator Based On An Interleaved Synchronous Mirror Delay Scheme , 1997, Symposium 1997 on VLSI Circuits.

[5]  E. Knoll,et al.  An interpolating clock synthesizer , 1996 .

[6]  Keng L. Wong,et al.  A PLL clock generator with 5 to 110 MHz lock range for microprocessors , 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[7]  Chih-Kong Ken Yang,et al.  A 0.8-/spl mu/m CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links , 1996 .

[8]  T. Matano,et al.  A 2.5 ns clock access 250 MHz 256 Mb SDRAM with a synchronous mirror delay , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[9]  J. Wei,et al.  A 660 MB/s interface megacell portable circuit in 0.3 /spl mu/m-0.7 /spl mu/m CMOS ASIC , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[10]  Yiu-Fai Chan,et al.  A portable digital DLL for high-speed CMOS interface circuits , 1999, IEEE J. Solid State Circuits.

[11]  Richard B. Watson,et al.  Clock Buffer Chip With Absolute Delay Regulation Over Process And Environmental Variations , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[12]  Thomas H. Lee,et al.  A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM , 1994, IEEE J. Solid State Circuits.

[13]  Keng L. Wong,et al.  A PLL clock generator with 5 to 110 MHz of lock range for microprocessors , 1992 .

[14]  Stefanos Sidiropoulos,et al.  A semidigital dual delay-locked loop , 1997, IEEE J. Solid State Circuits.

[15]  J.G. Maneatis,et al.  Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[16]  Takanori Saeki,et al.  A direct-skew-detect synchronous mirror delay for application-specific integrated circuits , 1999 .

[17]  Alain Greiner,et al.  A Portable Clock Multiplier Generator using Digital CMOS Standard Cells , 1995, ESSCIRC '95: Twenty-first European Solid-State Circuits Conference.