Minimizing peak power consumption during scan testing: test pattern modification with X filling heuristics

Scan architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we discuss the issues of excessive peak power consumption during scan testing. We show that taking care of high current levels during the test cycle (i.e. between launch and capture) is highly relevant to avoid noise phenomena such as IR-drop or ground bounce. We propose a solution based on power-aware assignment of don't care bits in deterministic test patterns. For ISCAS'89 and ITC'99 benchmark circuits, this approach reduces peak power during the test cycle up to 89% compared to a random filling solution

[1]  Patrick Girard,et al.  A gated clock scheme for low power scan-based BIST , 2001, Proceedings Seventh International On-Line Testing Workshop.

[2]  Atul K. Jain,et al.  Minimizing power consumption in scan testing: pattern generation and DFT techniques , 2004 .

[3]  Bashir M. Al-Hashimi,et al.  Power-constrained testing of VLSI circuits , 2003 .

[4]  Kwame Osei Boateng,et al.  BIST-aided scan test - a new method for test cost reduction , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[5]  Nur A. Touba,et al.  Controlling peak power during scan testing , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[6]  Kenneth M. Butler,et al.  A case study of ir-drop in structured at-speed testing , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[7]  Kozo Kinoshita,et al.  On low-capture-power test generation for scan testing , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[8]  裕幸 飯田,et al.  International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について － , 2004 .

[9]  Bashir M. Al-Hashimi,et al.  Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Arnaud Virazel,et al.  Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing , 2006, 2006 IFIP International Conference on Very Large Scale Integration.

[11]  Serge Pravossoudovitch,et al.  Peak Power Consumption During Scan Testing: Issue, Analysis and Heuristic Solution , 2005 .

[12]  Minesh B. Amin,et al.  Efficient compression and application of deterministic patterns in a logic BIST architecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[13]  R. Schaller,et al.  Technological innovation in the semiconductor industry: A case study of the International Technology Roadmap for Semiconductors (ITRS) , 2001, PICMET '01. Portland International Conference on Management of Engineering and Technology. Proceedings Vol.1: Book of Summaries (IEEE Cat. No.01CH37199).

[14]  L. Whetsel,et al.  An analysis of power reduction techniques in scan testing , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).