Shaving Retries with Sentinels for Fast Read over High-Density 3D Flash

High-density flash-memory chips are under tremendous demands with the exponential growth of data. At the same time, the slow read performance of these high-density flash-memory chips becomes a new challenge. In this work, we analyze the high raw bit error rates (RBER) issue by characterizing the error behaviours of 3D QLC flash-memory chips. A preferred read voltage to a QLC cell could vary among layers and might even change in a short period of time due to the temperature. A sentinel-cell approach is thus proposed to utilize the error characteristics among cells. We propose to infer the optimal read voltages of a wordline based on errors introduced on sentinel cells. An on-line calibration procedure is further presented to resolve the problem of possible non-uniform error distribution on some wordlines. With optimal voltages being inferred, the number of read retries will be significantly reduced. Experiments show that optimal read voltages can be instantly obtained in 94% cases on average over the evaluated QLC flash memory with at most 2 read retries, and with merely 0.2% space overheads for adopting sentinel cells. The number of read retries could be reduced by 82% on average, and the read performance can be improved by 74% on average through a series of extensive experiments over 3D TLC and QLC flash-memory chips.

[1]  Yixin Luo,et al.  Improving the reliability of chip-off forensic analysis of NAND flash memory devices , 2017, Digit. Investig..

[2]  Sung-Jin Choi,et al.  Comprehensive evaluation of early retention (fast charge loss within a few seconds) characteristics in tube-type 3-D NAND flash memory , 2016, 2016 IEEE Symposium on VLSI Technology.

[3]  Onur Mutlu,et al.  Threshold voltage distribution in MLC NAND flash memory: Characterization, analysis, and modeling , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[4]  Arif Merchant,et al.  Flash Reliability in Production: The Expected and the Unexpected , 2016, FAST.

[5]  Mahmut T. Kandemir,et al.  ZombieNAND: Resurrecting Dead NAND Flash for Improved SSD Longevity , 2014, 2014 IEEE 22nd International Symposium on Modelling, Analysis & Simulation of Computer and Telecommunication Systems.

[6]  Nanning Zheng,et al.  LDPC-in-SSD: making advanced error correction codes work effectively in solid state drives , 2013, FAST.

[7]  Paul H. Siegel,et al.  Towards minimizing read time for NAND flash , 2012, 2012 IEEE Global Communications Conference (GLOBECOM).

[8]  Sang Lyul Min,et al.  Design Tradeoffs for SSD Reliability , 2019, FAST.

[9]  Qiao Li,et al.  Access Characteristic Guided Read and Write Cost Regulation for Performance Improvement on Flash Memory , 2016, FAST.

[10]  Fei Wu,et al.  Characterizing 3D Charge Trap NAND Flash: Observations, Analyses and Applications , 2018, 2018 IEEE 36th International Conference on Computer Design (ICCD).

[11]  Jiesheng Wu,et al.  Lessons and Actions: What We Learned from 10K SSD-Related Storage System Failures , 2019, USENIX Annual Technical Conference.

[12]  Alessandro S. Spinelli,et al.  Reliability of NAND Flash Arrays: A Review of What the 2-D–to–3-D Transition Meant , 2019, IEEE Transactions on Electron Devices.

[13]  Il Han Park,et al.  A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory , 2018, IEEE Journal of Solid-State Circuits.

[14]  Jeong-Don Ihm,et al.  256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers , 2017, IEEE Journal of Solid-State Circuits.

[15]  Onur Mutlu,et al.  Data retention in MLC NAND flash memory: Characterization, optimization, and recovery , 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).

[16]  Frederic Sala,et al.  Dynamic Threshold Schemes for Multi-Level Non-Volatile Memories , 2012, IEEE Transactions on Communications.

[17]  Onur Mutlu,et al.  Errors in Flash-Memory-Based Solid-State Drives: Analysis, Mitigation, and Recovery , 2017, ArXiv.

[18]  Hsie-Chia Chang,et al.  A 45nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[19]  Myoungjun Chun,et al.  Exploiting Process Similarity of 3D Flash Memory for High Performance SSDs , 2019, MICRO.

[20]  Qiang Wu,et al.  A Large-Scale Study of Flash Memory Failures in the Field , 2015, SIGMETRICS 2015.

[21]  Onur Mutlu,et al.  Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation , 2018, SIGMETRICS.

[22]  Nikolas Ioannou,et al.  Reliability of 3D NAND flash memory with a focus on read voltage calibration from a system aspect , 2019, 2019 19th Non-Volatile Memory Technology Symposium (NVMTS).

[23]  Yi Fang,et al.  Neighbor-A-Posteriori Information Assisted Cell-State Adaptive Detector for NAND Flash Memory , 2019, IEEE Communications Letters.

[24]  Hiroshi Nakamura,et al.  13.5 A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology , 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

[25]  Chun Jason Xue,et al.  Constructing Large, Durable and Fast SSD System via Reprogramming 3D TLC Flash Memory , 2019, MICRO.

[26]  Fei Wu,et al.  Characterizing 3D Floating Gate NAND Flash , 2018, SIGMETRICS.

[27]  Hong Jiang,et al.  Exploring and Exploiting the Multilevel Parallelism Inside SSDs for Improved Performance and Endurance , 2013, IEEE Transactions on Computers.

[28]  Woopyo Jeong,et al.  13.2 A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique , 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

[29]  A. Goda 3-D NAND Technology Achievements and Future Scaling Perspectives , 2020, IEEE Transactions on Electron Devices.

[30]  Antony I. T. Rowstron,et al.  Migrating server storage to SSDs: analysis of tradeoffs , 2009, EuroSys '09.

[31]  Jie Liu,et al.  SSD Failures in Datacenters: What? When? and Why? , 2016, SYSTOR.

[32]  Zhiyuan Cheng,et al.  Improving 3D NAND Flash Memory Read Performance by Modeling the Read Offset , 2019, 2019 IEEE 19th International Conference on Communication Technology (ICCT).

[33]  Nikolaos Papandreou,et al.  Using adaptive read voltage thresholds to enhance the reliability of MLC NAND flash memory systems , 2014, GLSVLSI '14.

[34]  Thomas P. Parnell,et al.  Modelling of the threshold voltage distributions of sub-20nm NAND flash memory , 2014, 2014 IEEE Global Communications Conference.

[35]  Liang Shi,et al.  Sentinel Cells Enabled Fast Read for NAND Flash , 2019, HotStorage.

[36]  Onur Mutlu,et al.  HeatWatch: Improving 3D NAND Flash Memory Device Reliability by Exploiting Self-Recovery and Temperature Awareness , 2018, 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA).

[37]  Chun Jason Xue,et al.  Exploiting Asymmetric Errors for LDPC Decoding Optimization on 3D NAND Flash Memory , 2020, IEEE Transactions on Computers.