Formal performance evaluation of AMBA-based system-on-chip designs

The ARM Advanced Microcontroller Bus Architecture (AMBA) is a widely used interconnection standard for SoC design. In order to support high-speed pipelined data transfers, AMBA supports a rich set of bus signals, making the analysis of AMBA-based embedded systems a challenging proposition. This paper makes two main contributions to the analysis and evaluation of AMBA-based SoC designs. The first contribution is to provide a method for the performance analysis and evaluation of AMBA-based SoC designs using formal models. This method provides a way to obtain the end-to-end execution bounds of AMBA-based SoC designs, and guarantees the correctness of the results. The second contribution is to use these formal models to prove the functional correctness of the SoC designs. Using our formal models, we were able to uncover an ambiguous case in the AMBA specification that can lead to deadlocks. This case has not been previously documented by methods focused on AMBA protocol verification. Finally, we validate the proposed performance analysis approach by comparing results with a SystemC implementation of a digital camera case study.

[1]  E.M. Clarke,et al.  Verifying IP-core based system-on-chip designs , 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).

[2]  Wang Yi,et al.  Timed automata as task models for event-driven systems , 1999, Proceedings Sixth International Conference on Real-Time Computing Systems and Applications. RTCSA'99 (Cat. No.PR00306).

[3]  Thomas F. Melham,et al.  An AMBA-ARM7 Formal Verification Platform , 2003, ICFEM.

[4]  Tulika Mitra,et al.  Using formal techniques to debug the AMBA system-on-chip bus protocol , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[5]  Randal E. Bryant,et al.  Symbolic Boolean manipulation with ordered binary-decision diagrams , 1992, CSUR.

[6]  Marco Pistore,et al.  NuSMV 2: An OpenSource Tool for Symbolic Model Checking , 2002, CAV.

[7]  Arcot Sowmya,et al.  Synchronous protocol automata: a framework for modelling and verification of SoC communication architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[8]  Sudeep Pasricha.  Transaction level modeling of SoC with SystemC 2.0 , 2004 .

[9]  Rolf Ernst,et al.  A Formal Approach to MpSoC Performance Verification , 2003, Computer.

[10]  Daniel D. Gajski,et al.  SPECC: Specification Language and Methodology , 2000 .

[11]  David S. Taubman,et al.  High performance scalable image compression with EBCOT , 1999, Proceedings 1999 International Conference on Image Processing (Cat. 99CH36348).

[12]  John A. Clark,et al.  Holistic schedulability analysis for distributed hard real-time systems , 1994, Microprocess. Microprogramming.

[13]  Edmund M. Clarke,et al.  Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic , 1981, Logic of Programs.

[14]  Gerard J. Holzmann,et al.  The SPIN Model Checker - primer and reference manual , 2003 .

[15]  Rachel Cardell-Oliver,et al.  Analysis of Scheduling Behaviour using Generic Timed Automata , 2001, Electron. Notes Theor. Comput. Sci..

[16]  Amit Goel,et al.  Formal verification of an IBM CoreConnect processor local bus arbiter core , 2000, DAC.

[17]  Hasan Amjad.  Verification of AMBA Using a Combination of Model Checking and Theorem Proving , 2006, Electron. Notes Theor. Comput. Sci..

[18]  Kenneth L. McMillan,et al.  The SMV System , 1993 .

[19]  Edward A. Lee.  The problem with threads , 2006, Computer.

[20]  Fadi J. Kurdahi,et al.  A Scalable Embedded JPEG2000 Architecture , 2005, SAMOS.

[21]  Nikil D. Dutt,et al.  Extending the transaction level modeling approach for fast communication architecture exploration , 2004, Proceedings. 41st Design Automation Conference, 2004..