A 1.0-V V/sub DD/ CMOS active-pixel sensor with complementary pixel architecture and pulsewidth modulation fabricated with a 0.25-/spl mu/m CMOS process

In this paper, an architecture to design a CMOS active-pixel sensor (APS) in an extremely low-voltage environment imposed by advanced CMOS technology is proposed. A complementary active pixel sensor (CAPS) architecture is developed to allow a CMOS active pixel to operate at a voltage below 1 V V/sub DD/ without using bootstrapping techniques. A fixed voltage deference (FVD) method with correlated double sampling is used to increase the dynamic range of the readout circuit. Both the CAPS and FVD readout circuits together, with an 8-b analog-to-digital converter, are implemented in a commercially available 0.25-/spl mu/m, single-poly and five-metal CMOS process. Measurement results show that the circuit is functional at a V/sub DD/ below 1 V with 15-dB added dynamic range compared with a conventional CMOS APS architecture.

[1]  Takeo Kanade,et al.  A VLSI sorting image sensor: global massively parallel intensity-to-time processing for low-latency adaptive vision , 1999, IEEE Trans. Robotics Autom..

[2]  Eric R. Fossum,et al.  CMOS image sensors: electronic camera on a chip , 1995, Proceedings of International Electron Devices Meeting.

[3]  M. Chan,et al.  A low voltage hybrid bulk/SOI CMOS active pixel image sensor , 2001, IEEE Electron Device Letters.

[4]  P. Agnello,et al.  CMOS active pixel image sensors fabricated using a 1.8 V, 0.25 /spl mu/m CMOS technology , 1996, International Electron Devices Meeting. Technical Digest.

[5]  Hon-Sum Philip Wong.  CMOS image sensors-recent advances and device scaling considerations , 1997 .

[6]  E.R. Fossum,et al.  A 1.2 V micropower CMOS active pixel image sensor for portable applications , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[7]  Xinqiao Liu,et al.  A 10000 frames/s CMOS digital pixel sensor , 2001, IEEE J. Solid State Circuits.