Conventional Architecture of Turbo Decoder

When digital circuits and storage elements are exploited to perform the theoretical algorithm, we should pay attention to how the cycle-based process and resource limitation affect the turbo decoding. During the implementation, the hardware cost is of top priority. Our targets are usually fast processing speed and great decoding performance at the least expense of hardware. Of course those techniques toward lower complexity in the previous chapter will be applied. The practical design contains several functional units for the major computations in the simplified algorithm; besides, it needs a few control units to handle the data flow for the sliding window method and the message propagation between two constituent codes. These internal devices will run a variety of arithmetic operations. Among all the operations, the multiplication and division should be avoided because their corresponding circuits take much longer execution time and much larger hardware resource. In this chapter, we introduce the major component circuits of a practical turbo decoder at first. Then we shift the focus to the conventional architecture of the SISO decoder as well as its processing schedule. Based on such a prototype, the design issues about replacing the floating-point data with fixed-point data are highlighted. It is possible that the loss of precision gives rise to performance degradation. On the other hand, the bit number for data expression, also called data width, dominates the hardware cost. Thus, the choice of adequate data width is dependent on both the required performance and acceptable overhead. The subsequent discussions address the potential overflow problem and show the effects of several solutions. At the end of the chapter, two modified SISO decoders that have advantages such as shorter latency or less hardware over the conventional one are presented.