Steiner Routing for 3D IC

In this chapter, we study a performance and thermal-aware Steiner routing algorithm for 3D stacked ICs. Our algorithm consists of two steps: tree construction and tree refinement. Our tree construction algorithm builds a delay-oriented Steiner tree under a given thermal profile. We show that our 3D tree construction involves minimization of two-variable Elmore delay function. In our tree refinement algorithm, we reposition the through-silicon-vias (TSVs) used in existing Steiner trees while preserving the original routing topology for further thermal optimization under performance constraint. We employ a novel scheme to relax the initial NLP formulation to ILP and consider all TSV from all nets simultaneously. Our tree construction algorithm outperforms the popular 3D-maze routing by 52% in terms of performance at the cost of 15% wirelength and 6% TSV count increase for four-die stacking. In addition, our TSV relocation results in 9% maximum temperature reduction at no additional area cost. We also provide extensive experimental results including (i) the wirelength and delay distribution of various types of 3D interconnects, (ii) the impact of TSV RC parasitics on routing and TSV relocation, and (iii) the impact of various bonding styles on routing and TSV relocation. Lastly, we provide results on two-die stacking.

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