Programmable FM Receiver for Hearing-Aid Applications in 0.25µm CMOS

= 100mV and Vdd = 0.9V which is much too high. Figure 24.2.3b proposes an optimized divider that improves the PSRR by reduc- ing the absolute delay time. The delay from input to output is now determined by a 2-input NAND instead of the divider. This results in 26dB less modulation of the LO for the same condi- tions as above. Since the phase frequency detector triggers on falling input edges only, the 75% duty cycle of the divider output does not introduce any timing problems. The implementation of the divide-by-8-to-15 prescaler, shown in Fig. 24.2.4, is more complex but it follows the same working principle. The classic output signal d3 is combined with the input signal such that the position of the output signal edges is directly determined by the input with an as low as possible extra delay.