Analysis of the Effect of Temperature and Vdd on Leakage Current in Conventional 6TSRAM BitCell at 90nm and 65nm Technology

The increased demand for battery operated portable semiconductor applications and continuous scaling of CMOS devices, results high packaging density but increases the importance of power even more noticeable for a new class of energy constrained systems. Recent Low-Power VLSI design interest is in operating the CMOS circuits with power supply voltage below the transistor threshold operation. As subthreshold circuits can allow ultra-low power designs to be fabricated on modern CMOS process technology, sub-threshold operation is applicable to wide range of applications ranging from wireless devices, biomedical applications, spacecraft related applications, etc. Lowering the supply voltage to reduce power consumption is one of the choices of the designers for designing low power SRAM circuits. For mobile/multimedia applications of SRAMs, there is a need to reduce standby leakage current while keeping memory cell data. In technology beyond 130nm low-power SRAM is severely complicated by intra die-variations and leakage power. For SRAM cells, leakage reduction has been obtained with low supply voltages and high threshold (HVT) transistors. In this work we have simulated a conventional 6T SRAM cell and analyzed the effect of the leakage and standby currents of 6T cell with respect to various supply voltage (Vdd) and operating temperatures at deep sub-micron technologies, i.e., 90nm and 65nm CMOS process. Here, the effect of temperature is observed on leakage currents at different supply voltages. As the temperature increases for 40C to 100C, it is observed that the leakage goes upto 90% in 90nm and 89% in 65nm at Vdd of 1V and 0.5V, respectively.