Input waveform slope effects in CMOS delays

Slow input ramp effects in delay evaluation on CMOS structures are considered. Corrections of previously defined closed-form equations are proposed, allowing accurate evaluation of delays in a large range of configurations. The expressions obtained remain sufficiently manageable to be used in an automatic data-path sizing tool. >

[1]  William H. Kao,et al.  Algorithms for Automatic Transistor Sizing in CMOS Digital Circuits , 1985, DAC 1985.

[2]  D. Deschacht,et al.  Explicit formulation of delays in CMOS VLSI , 1987 .

[3]  D. Deschacht,et al.  Explicit formulation of delays in CMOS data paths , 1988 .

[4]  Chin-Fu Chen,et al.  A Fast-Timing Simulator for Digital MOS Circuits , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.