Epi defined (ED) FinFET: An alternate device architecture for high mobility Ge channel integration in PMOSFET

Band to band tunneling (BTBT) is a major challenge in Ge FinFETs due to its smaller band gap. Narrow fin widths reduce BTBT due to quantum confinement (QC). However, Line Edge Roughness (LER) on narrower fins causes large VT variability. Previously, we have proposed an architecture named Epitaxially Defined (ED) FinFET to reduce VT variability due to LER wherein channel depletion is defined by low doped highly uniform epitaxy (thus named Epi Defined FinFET) (epi-thickness non uniformity<;2%) over a thick highly doped Si fin instead of lithography based patterning subject to LER (non-uniformity<;50% i.e. 2nm LER on a 4nm fin). In the present work, we propose integration of Ge into EDFinFET architecture in which Ge (or SiGe) is grown on top of Si fin. Proposed structure shows 10× reduction in LER based VT variability in comparison to FinFETs. Valence band QC in gate oxide/Ge/Si stack is used to control BTBT. Biaxial stress in thin Ge epitaxially grown on Si results in 27% higher ION. Thin Ge film required is lower than critical defect free thickness of Ge epitaxy on Si. Hence defect free Ge integration into FinFET architecture in enabled. We also show that EDFinFET can enable multiple VT just by the application of a bias at the body terminal.