Techniques for improved placement-coupled logic replication

Several recent papers have utilized logic replication driven by placement-level timing analysis for improving clock period (e.g., [1], [8], [18], and [2]). All of these papers demonstrated, through various optimization strategies, the potential of the basic technique of replication. In this paper we propose a number of techniques aimed at more fully realizing this potential within the framework employed in [8]. As reported in [7], there are situations in which the approach of [8] fails to yield significant additional improvement due largely to the effects of reconvergence in the netlist. We suggest the use of rectilinear Steiner arborescence embedding as a tool for overcoming this limitation. We also propose techniques for fanout partitioning and cell relocation which are cognizant of both wirelength and timing impact for improved solution quality. We report the effect of other techniques including new replication cost computation, lower-bounding of achievable clock period, and wirelength estimation. We have implemented and experimented with these techniques in FPGA domain. In many cases we were able to approach a fixed flip-flop lower-bound on achievable clock period. Promising experimental results are reported with average 17.4% (up to 39.9%) delay reduction compared with the timing-driven placement from VPR[16] and average 9.3% (up to 37.2%) reduction compared with the basic fanin tree embedder from [8].