Fast energy aware application specific Network-on-Chip topology generator

Network-on-Chip(NoC) has been proposed as a solution for addressing the design challenges of future high-performance nanoscale architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. In this paper, fast deterministic methodologies are proposed for synthesis of energy aware communication architecture along with corresponding routing tables of an application specific NoC where the traffic communication traffic characteristics can be well characterized at design time.

[1]  William J. Dally,et al.  Deadlock-Free Message Routing in Multiprocessor Interconnection Networks , 1987, IEEE Transactions on Computers.

[2]  Yeh-Ching Chung,et al.  An efficient deadlock-free tree-based routing algorithm for irregular wormhole-routed networks based on the turn model , 2004 .

[3]  Wayne H. Wolf,et al.  TGFF: task graphs for free , 1998, Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98).

[4]  Sharad Malik,et al.  Orion: a power-performance simulator for interconnection networks , 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..

[5]  Radu Marculescu,et al.  Energy- and performance-aware mapping for regular NoC architectures , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Federico Silla,et al.  High-Performance Routing in Networks of Workstations with Irregular Topology , 2000, IEEE Trans. Parallel Distributed Syst..

[7]  Krishnan Srinivasan,et al.  Layout aware design of mesh based NoC architectures , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

[8]  William J. Dally,et al.  Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.

[9]  Hideharu Amano,et al.  L-turn routing: an adaptive routing in irregular networks , 2001, International Conference on Parallel Processing, 2001..

[10]  Lasse Natvig.  High-level architectural simulation of the Torus Routing Chip , 1997, Proceedings of Meeting on Verilog HDL (IVC/VIUF'97).

[11]  Jie Wu,et al.  Deadlock-Free Routing In Irregular Networks Using Prefix Routing , 2003, Parallel Process. Lett..

[12]  Michael Burrows,et al.  Autonet: A High-Speed, Self-Configuring Local Area Network Using Point-to-Point Links , 1991, IEEE J. Sel. Areas Commun..

[13]  Antonio Robles,et al.  Efficient Adaptive Routing in Networks of Workstations with Irregular Topology , 1997, CANPC.

[14]  Radu Marculescu,et al.  Key research problems in NoC design: a holistic perspective , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[15]  Yao-Wen Chang,et al.  B*-Trees: a new representation for non-slicing floorplans , 2000, DAC.

[16]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[17]  Radu Marculescu,et al.  Energy-aware mapping for tile-based NoC architectures under performance constraints , 2003, ASP-DAC '03.

[18]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[19]  Radu Marculescu,et al.  Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures , 2003, DATE.

[20]  Lionel M. Ni,et al.  The turn model for adaptive routing , 1992, ISCA '92.