A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash

The embedded Flash technology can be subject to complex defects creating functional faults. In this paper, we describe the different steps in the electrical modeling of 2T-FLOTOX core-cells for a good understanding of failure mechanisms. At first, we present a first order electrical model of 2T-FLOTOX core-cells which is characterized and compared with silicon data measurements based on the ATMEL 0.15 µm eFlash technology. Next, we propose a study of resistive defect injections in eFlash memories to show the interest of the proposed simulation model. At the end of the paper, a table summarizes the functional fault models for different resistive defect configurations and experimental set-ups. According to these first results and with additional analysis on actual defects presented in [3] we are then able to enhance existing test solutions for eFlash testing.

[1]  Kiyoo Itoh,et al.  Vlsi Memory Chip Design , 2006 .

[3]  Approved June,et al.  IEEE Standard Definitions and Characterization of Floating Gate Semiconductor Arrays , 1991 .

[4]  A. Concannon,et al.  Development and application of a macro model for flash EEPROM design , 2000, Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541).

[5]  Jean Michel Portal,et al.  Floating-gate EEPROM cell model based on MOS model 9 , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[6]  M. Lenzlinger,et al.  Fowler‐Nordheim Tunneling into Thermally Grown SiO2 , 1969 .

[7]  John F. Dickson,et al.  On-Chip High-Voltage Generation in Integrated Circuits Using an Improved Multiplier Technique , 1976 .

[8]  Arnaud Virazel,et al.  Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window , 2007, 25th IEEE VLSI Test Symposium (VTS'07).

[9]  Piero Olivo,et al.  Flash memory cells-an overview , 1997, Proc. IEEE.

[10]  Arnaud Virazel,et al.  An overview of failure mechanisms in embedded flash memories , 2006, 24th IEEE VLSI Test Symposium.

[11]  Tetsuo Endoh,et al.  Reliability issues of flash memory cells , 1993, Proc. IEEE.

[12]  Kewal K. Saluja,et al.  Flash memory disturbances: modeling and test , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[13]  Yea-Ling Horng,et al.  A realistic fault model for flash memories , 2000, Proceedings of the Ninth Asian Test Symposium.

[14]  Kewal K. Saluja,et al.  Simulating program disturb faults in flash memories using SPICE compatible electrical model , 2003 .