A $148fs_{rms}$ Integrated Noise 4 MHz Bandwidth Second-Order $\Delta\Sigma$ Time-to-Digital Converter With Gated Switched-Ring Oscillator

This paper presents a second-order ΔΣ time-to-digital converter (TDC) by using a switched-ring oscillator (SRO) and a gated switched-ring oscillator (GSRO). Unlike conventional multi-stage noise-shaping (MASH) TDC using SROs, the proposed TDC does not require complex calibration to compensate for the error from frequency difference between the oscillators. Furthermore, the performance of the proposed TDC is analyzed, including non-idealities such as phase noise, mismatch, and PVT variations. The prototype 1-1 MASH TDC achieves 148 f srms integrated noise in 4 MHz signal bandwidth at 400 MS/s while consuming 6.55 mW in a 65 nm CMOS process.

[1]  Jae-Yoon Sim,et al.  A 2 GHz fractional-N digital PLL with 1b noise shaping ΔΣ TDC , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[2]  Paul Leroux,et al.  1-1-1 MASH $\Delta \Sigma$ Time-to-Digital Converters With 6 ps Resolution and Third-Order Noise-Shaping , 2012, IEEE Journal of Solid-State Circuits.

[3]  Antonio Liscidini,et al.  Time to digital converter based on a 2-dimensions Vernier architecture , 2009, 2009 IEEE Custom Integrated Circuits Conference.

[4]  SeongHwan Cho,et al.  A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register , 2014, IEEE Journal of Solid-State Circuits.

[5]  Tadahiro Kuroda,et al.  A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS , 2012, IEEE Journal of Solid-State Circuits.

[6]  K. Nose,et al.  A 1-ps Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling , 2006, IEEE Journal of Solid-State Circuits.

[7]  Jaewook Kim,et al.  A Time-Domain High-Order MASH $\Delta\Sigma$ ADC Using Voltage-Controlled Gated-Ring Oscillator , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  A. Abidi,et al.  A 9b, 1.25ps Resolution Coarse-Fine Time-to-Digital Converter in 90nm CMOS that Amplifies a Time Residue , 2007, 2007 IEEE Symposium on VLSI Circuits.

[9]  Amr Elshazly,et al.  A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators , 2012, 2012 IEEE International Solid-State Circuits Conference.

[10]  SeongHwan Cho,et al.  A 148fsrms integrated noise 4MHz bandwidth all-digital second-order ΔΣ time-to-digital converter using gated switched-ring oscillator , 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

[11]  Jae-Yoon Sim,et al.  A 1.25 ps Resolution 8b Cyclic TDC in 0.13 $\mu$m CMOS , 2012, IEEE Journal of Solid-State Circuits.

[12]  Michael P. Flynn,et al.  A 9-bit, 14 μW and 0.06 mm $^{2}$ Pulse Position Modulation ADC in 90 nm Digital CMOS , 2010, IEEE Journal of Solid-State Circuits.

[13]  Shintaro Izumi,et al.  A 61-dB SNDR 700 µm2 second-order all-digital TDC with low-jitter frequency shift oscillators and dynamic flipflops , 2012, 2012 Symposium on VLSI Circuits (VLSIC).

[14]  Un-Ku Moon,et al.  A 71dB dynamic range third-order ΔΣ TDC using charge-pump , 2012, 2012 Symposium on VLSI Circuits (VLSIC).

[15]  Paul Leroux,et al.  1-1-1 MASH ∆ Σ Time-to-Digital Converters with 6 ps Resolution and Third-Order Noise-Shaping , 2012 .

[16]  Jae-Yoon Sim,et al.  A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-µm CMOS , 2013, IEEE Journal of Solid-State Circuits.

[17]  Amr Elshazly,et al.  A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth , 2010, IEEE Custom Integrated Circuits Conference 2010.

[18]  Stephan Henzler,et al.  90nm 4.7ps-Resolution 0.7-LSB Single-Shot Precision and 19pJ-per-Shot Local Passive Interpolation Time-to-Digital Converter with On-Chip Characterization , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[19]  M.Z. Straayer,et al.  A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping , 2009, IEEE Journal of Solid-State Circuits.

[20]  Jaewook Kim,et al.  Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.