40-Gb/s High-Gain Distributed Amplifiers With Cascaded Gain Stages in 0.18-$\mu{\hbox {m}}$ CMOS

A novel circuit topology for high-gain distributed amplifiers is presented in this study. Based on the conventional distributed architecture, the gain cells are realized by cascading cas- code stages for gain enhancement. In addition, the stagger-tuning technique is extensively utilized in the design of the cascode stages as well as the cascaded stages, leading to significant improvement in terms of the operating bandwidth and the gain flatness. With the proposed circuit architecture, two amplifiers are implemented in a standard 0.18-mum CMOS technology. The amplifier with a 3 times 3 configuration exhibits a gain of 16.2 dB and a 3-dB bandwidth of 33.4 GHz, while the one in a form of 2 times 4 demonstrates a gain of 20 dB and a bandwidth of 39.4 GHz. Consuming a dc power of 260 mW from a 2.8-V supply voltage, both circuits provide clear eye-opening with a pseudorandom bit sequence (PRBS) at 40 Gb/s.

[1]  Huei Wang,et al.  A 70GHz cascaded multi-stage distributed amplifier in 90nm CMOS technology , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[2]  C. Nguyen,et al.  Low-power-consumption and high-gain CMOS distributed amplifiers using cascade of inductively coupled common-source gain cells for UWB systems , 2006, IEEE Transactions on Microwave Theory and Techniques.

[3]  Huei Wang,et al.  A miniature 25-GHz 9-dB CMOS cascaded single-stage distributed amplifier , 2004, IEEE Microwave and Wireless Components Letters.

[4]  Ali Hajimiri,et al.  Multi–pole bandwidth enhancement technique for trans-impedance amplifiers , 2002 .

[5]  Kambiz Moez,et al.  A 10dB 44GHz Loss-Compensated CMOS Distributed Amplifier , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[6]  Lijun Li,et al.  A 34 Gb/s Distributed 2:1 MUX and CMU Using 0.18$muhbox m$CMOS , 2006, IEEE Journal of Solid-State Circuits.

[7]  Kuo-Liang Deng,et al.  Design and analysis of DC-to-14-GHz and 22-GHz CMOS cascode , 2004 .

[8]  Shen-Iuan Liu,et al.  A 0.1-25.5-GHz Differential Cascaded-Distributed Amplifier in 0.18- μm CMOS Technology , 2005, 2005 IEEE Asian Solid-State Circuits Conference.

[9]  Michael M. Green,et al.  A 34 Gb / s Distributed 2 : 1 MUX and CMU Using 0 . 18 m CMOS , 2006 .

[10]  F. Zhang,et al.  Low-power programmable gain CMOS distributed LNA , 2006, IEEE Journal of Solid-State Circuits.

[11]  N.G. Tarr,et al.  A 27 GHz fully integrated CMOS distributed amplifier using coplanar waveguides , 2004, 2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers.

[12]  Jean-Olivier Plouchart,et al.  Amplifier in a 0.12µm SOI CMOS , 2004 .

[13]  Liang-Hung Lu,et al.  A 9.5-dB 50-GHz Matrix Distributed Amplifier in 0.18-/spl mu/m CMOS , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

[14]  Liang-Hung Lu,et al.  40-Gb / s High-Gain Distributed Amplifiers With Cascaded Gain Stages in 0 . 18-m CMOS , 2009 .

[15]  H. Shigematsu,et al.  4 40 Gb / s CMOS Distributed Amplifier for Fiber-Optic Communication Systems , 2001 .

[16]  Deog-Kyoon Jeong,et al.  Circuit techniques for a 40Gb/s transmitter in 0.13/spl mu/m CMOS , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[17]  M. Rodwell,et al.  40Gb/s CMOS distributed amplifier for fiber-optic communication systems , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[18]  D. Yamazaki,et al.  40Gb/s 4:1 MUX/1:4 DEMUX in 90nm standard CMOS , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[19]  Payam Heydari,et al.  A performance optimized CMOS distributed LNA for UWB receivers , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[20]  J. Lee,et al.  A 40 Gb/s clock and data recovery circuit in 0.18 /spl mu/m CMOS technology , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[21]  D.J. Allstot,et al.  Bandwidth Extension Techniques for CMOS Amplifiers , 2006, IEEE Journal of Solid-State Circuits.

[22]  Kuo-Liang Deng,et al.  A 0.6-22-GHz broadband CMOS distributed amplifier , 2003, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003.

[23]  Ahmad Yazdi,et al.  Differential Non-Uniform Downsized Distributed Amplifier , 2005 .

[24]  Behzad Razavi,et al.  40-Gb/s amplifier and ESD protection circuit in 0.18-/spl mu/m CMOS technology , 2004, IEEE Journal of Solid-State Circuits.

[25]  Arpad L. Scholtz,et al.  40-Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120-nm standard CMOS , 2003 .

[26]  M. Sherony,et al.  A 12dBm 320GHz GBW distributed amplifier in a 0.12/spl mu/m SOI CMOS , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[27]  Stephen P. Boyd,et al.  Bandwidth extension in CMOS with optimized on-chip inductors , 2000, IEEE Journal of Solid-State Circuits.

[28]  Behzad Razavi,et al.  A 40 Gb/s clock and data recovery circuit in 0.18 μm CMOS technology , 2003 .

[29]  A. Hajimiri,et al.  Bandwidth enhancement for transimpedance amplifiers , 2004, IEEE Journal of Solid-State Circuits.