Low-power 10-bit 100 MS/s pipelined ADC in digital CMOS technology

A 10-bit pipelined analogue-to-digital converter (ADC) at a sampling rate of 100 MS/s utilising only metal–oxide–semiconductor (MOS) transistors is presented and designed in 1.8 V 0.18 μm standard digital complementary MOS (CMOS) n-well technology. The internal gain of value 2 of the intermediate stages is achieved by using a charge-pump-based concept that avoids the use of power-area inefficient operational amplifier. All the capacitors are realised by capacitors implemented by metal–oxide–semiconductor field-effect transistors (MOSCAPs) that allows easy integration with any inexpensive standard digital CMOS technology, and altogether giving low area-power-cost solution. A low DC gain CMOS differential amplifier in source follower configuration is used and low gain effects are calibrated digitally in the background. Peak differential non-linearity (DNL) improves from −1/+0.27 least significant bit (LSB) to −0.43/+0.57 LSB and peak integral non-linearity (INL) is reduced from −9.56/+9.3 LSB to within range of ±0.5 LSB after calibration. Also signal-to-noise plus distortion ratio (SNDR) and spurious-free dynamic range (SFDR) increase to 65.4 and 72.08 dB, respectively, after calibration.

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